Issued Patents All Time
Showing 226–250 of 340 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9876113 | Method for improving transistor performance through reducing the salicide interface resistance | Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann | 2018-01-23 |
| 9859424 | Techniques for integration of Ge-rich p-MOS source/drain contacts | Glenn A. Glass, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi | 2018-01-02 |
| 9859368 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more | 2018-01-02 |
| 9842928 | Tensile source drain III-V transistors for mobility improved n-MOS | Glenn A. Glass, Chandra S. Mohapatra | 2017-12-12 |
| 9812524 | Nanowire transistor devices and forming techniques | Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Daniel B. Aubertine | 2017-11-07 |
| 9793373 | Field effect transistor structure with abrupt source/drain junctions | Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan | 2017-10-17 |
| 9754940 | Self-aligned contact metallization for reduced contact resistance | Glenn A. Glass, Tahir Ghani | 2017-09-05 |
| 9735270 | Semiconductor transistor having a stressed channel | Robert S. Chau, Tahir Ghani, Kaizad Mistry | 2017-08-15 |
| 9728464 | Self-aligned 3-D epitaxial structures for MOS device fabrication | Glenn A. Glass, Daniel B. Aubertine, Gaurav Thareja, Tahir Ghani | 2017-08-08 |
| 9722023 | Selective germanium P-contact metalization through trench | Glenn A. Glass, Tahir Ghani | 2017-08-01 |
| 9705000 | III-V layers for n-type and p-type MOS source-drain contacts | Glenn A. Glass, Tahir Ghani | 2017-07-11 |
| 9680016 | Method for improving transistor performance through reducing the salicide interface resistance | Boyan Boyanov, Glenn A. Glass, Thomas Hoffmann | 2017-06-13 |
| 9660078 | Enhanced dislocation stress transistor | Cory E. Weber, Mark Liu, Hemant Deshpande, Daniel B. Aubertine | 2017-05-23 |
| 9653584 | Pre-sculpting of Si fin elements prior to cladding for transistor channel applications | Glenn A. Glass, Daniel B. Aubertine, Subhash M. Joshi | 2017-05-16 |
| 9640634 | Field effect transistor structure with abrupt source/drain junctions | Robert S. Chau, Patrick Morrow, Chia-Hong Jan, Paul Packan | 2017-05-02 |
| 9633835 | Transistor fabrication technique including sacrificial protective layer for source/drain at contact location | Glenn A. Glass, Michael Jackson, Michael L. Hattendorf, Subhash M. Joshi | 2017-04-25 |
| 9627384 | Transistors with high concentration of boron doped germanium | Glenn A. Glass, Tahir Ghani, Ravi Pillarisetty, Niloy Mukherjee, Jack T. Kavalieros +3 more | 2017-04-18 |
| 9614060 | Nanowire transistor with underlayer etch stops | Seiyon Kim, Daniel B. Aubertine, Kelin J. Kuhn | 2017-04-04 |
| 9583491 | CMOS nanowire structure | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Annalisa Cappellani, Stephen M. Cea +2 more | 2017-02-28 |
| 9490364 | Semiconductor transistor having a stressed channel | Robert S. Chau, Tahir Ghani, Kaizad Mistry | 2016-11-08 |
| 9484447 | Integration methods to fabricate internal spacers for nanowire devices | Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more | 2016-11-01 |
| 9484432 | Contact resistance reduction employing germanium overlayer pre-contact metalization | Glenn A. Glass, Tahir Ghani | 2016-11-01 |
| 9437710 | Method for improving transistor performance through reducing the salicide interface resistance | Boyan Boyanov, Glenn A. Glass, Thomas Hoffman | 2016-09-06 |
| 9437691 | Column IV transistors for PMOS integration | Glenn A. Glass | 2016-09-06 |
| 9397102 | III-V layers for N-type and P-type MOS source-drain contacts | Glenn A. Glass, Tahir Ghani | 2016-07-19 |