AM

Anand S. Murthy

IN Intel: 329 patents #17 of 30,777Top 1%
DP Daedalus Prime: 5 patents #1 of 21Top 5%
SO Sony: 4 patents #8,966 of 25,231Top 40%
TR Tahoe Research: 2 patents #16 of 215Top 8%
📍 Portland, OR: #9 of 9,213 inventorsTop 1%
🗺 Oregon: #17 of 28,073 inventorsTop 1%
Overall (All Time): #951 of 4,157,543Top 1%
340
Patents All Time

Issued Patents All Time

Showing 201–225 of 340 patents

Patent #TitleCo-InventorsDate
10373977 Transistor fin formation via cladding on sacrificial core Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Benjamin Chu-Kung +4 more 2019-08-06
10340374 High mobility field effect transistors with a retrograded semiconductor source/drain Gilbert Dewey, Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Sean T. Ma +2 more 2019-07-02
10304927 Selective germanium p-contact metalization through trench Glenn A. Glass, Tahir Ghani 2019-05-28
10297670 Contact resistance reduction employing germanium overlayer pre-contact metalization Glenn A. Glass, Tahir Ghani 2019-05-21
10290709 Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces Glenn A. Glass, Chandra S. Mohapatra, Tahir Ghani, Willy Rachmady, Gilbert Dewey +2 more 2019-05-14
10283589 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2019-05-07
10243078 Carrier confinement for high mobility channel devices Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +3 more 2019-03-26
10229997 Indium-rich NMOS transistor channels Chandra S. Mohapatra, Glenn A. Glass, Tahir Ghani, Willy Rachmady, Jack T. Kavalieros +3 more 2019-03-12
10211208 High-mobility semiconductor source/drain spacer Gilbert Dewey, Matthew V. Metz, Tahir Ghani, Willy Rachmady, Chandra S. Mohapatra +2 more 2019-02-19
10153372 High mobility strained channels for fin-based NMOS transistors Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Willy Rachmady +1 more 2018-12-11
10147817 Techniques for integration of Ge-rich p-MOS source/drain Glenn A. Glass, Tahir Ghani, Ying-Feng PANG, Nabil G. Mistkawi 2018-12-04
10141311 Techniques for achieving multiple transistor fin dimensions on a single die Glenn A. Glass 2018-11-27
10121856 Integration methods to fabricate internal spacers for nanowire devices Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more 2018-11-06
10109711 CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Kelin J. Kuhn +1 more 2018-10-23
10109628 Transistor device with gate control layer undercutting the gate dielectric Nick Lindert, Glenn A. Glass 2018-10-23
10090383 Column IV transistors for PMOS integration Glenn A. Glass 2018-10-02
10084087 Enhanced dislocation stress transistor Cory E. Weber, Mark Liu, Hemant Deshpande, Daniel B. Aubertine 2018-09-25
10084043 High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani +4 more 2018-09-25
10074573 CMOS nanowire structure Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Annalisa Cappellani, Stephen M. Cea +2 more 2018-09-11
10014412 Pre-sculpting of Si fin elements prior to cladding for transistor channel applications Glenn A. Glass, Daniel B. Aubertine, Subhash M. Joshi 2018-07-03
9997414 Ge/SiGe-channel and III-V-channel transistors on the same die Glenn A. Glass, Karthik Jambunathan 2018-06-12
9966440 Tin doped III-V material contacts Glenn A. Glass, Michael Jackson, Harold W. Kennel 2018-05-08
9929273 Apparatus and methods of forming fin structures with asymmetric profile Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi +3 more 2018-03-27
9893149 High mobility strained channels for fin-based transistors Stephen M. Cea, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros +1 more 2018-02-13
9882009 High resistance layer for III-V channel deposited on group IV substrates for MOS transistors Glenn A. Glass 2018-01-30