Issued Patents All Time
Showing 176–200 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10199480 | Controlling self-aligned gate length in vertical transistor replacement gate flow | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2019-02-05 |
| 10199464 | Techniques for VFET top source/drain epitaxy | Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Ruilong Xie, Chun-Chen Yeh | 2019-02-05 |
| 10177237 | Etch stop for airgap protection | Kangguo Cheng, Ruilong Xie | 2019-01-08 |
| 10177223 | FinFET with reduced parasitic capacitance | Kangguo Cheng, Darsen D. Lu, Xin Miao | 2019-01-08 |
| 10170594 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2019-01-01 |
| 10170588 | Method of forming vertical transport fin field effect transistor with high-K dielectric feature uniformity | Chun Wing Yeung, Chen Zhang | 2019-01-01 |
| 10170583 | Forming a gate contact in the active area | Kangguo Cheng, Ruilong Xie | 2019-01-01 |
| 10170582 | Uniform bottom spacer for vertical field effect transistor | Michael P. Belyansky, Cheng Chi, Ekmini Anuja De Silva | 2019-01-01 |
| 10170574 | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts | Hiroaki Niimi, Shariq Siddiqui | 2019-01-01 |
| 10170558 | Localized and self-aligned punch through stopper doping for finFET | Effendi Leobandung | 2019-01-01 |
| 10170551 | Sidewall image transfer nanosheet | Effendi Leobandung | 2019-01-01 |
| 10170479 | Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors | Kangguo Cheng, Zuoguang Liu, Sanjay C. Mehta | 2019-01-01 |
| 10170319 | Forming a contact for a tall fin transistor | Kangguo Cheng, Ruilong Xie | 2019-01-01 |
| 10164110 | Finfet including improved epitaxial topology | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2018-12-25 |
| 10157908 | Electrostatic discharge devices and methods of manufacture | Huiming Bu, Junjun Li, Theodorus E. Standaert | 2018-12-18 |
| 10158003 | Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins | Kangguo Cheng, Zuoguang Liu, Ruilong Xie | 2018-12-18 |
| 10158021 | Vertical pillar-type field effect transistor and method | Ruilong Xie, Kangguo Cheng | 2018-12-18 |
| 10157798 | Uniform bottom spacers in vertical field effect transistors | Cheng Chi, Min Gyu Sung, Ruilong Xie | 2018-12-18 |
| 10153201 | Method for making a dipole-based contact structure to reduce the metal-semiconductor contact resistance in MOSFETs | Huiming Bu, Hui-feng Li, Vijay Narayanan, Hiroaki Niimi | 2018-12-11 |
| 10147815 | Fully silicided linerless middle-of-line (MOL) contact | Joshua M. Rubin | 2018-12-04 |
| 10141308 | Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices | Praneet Adusumilli, Oleg Gluschenkov, Dechao Guo, Zuoguang Liu, Rajasekhar Venigalla | 2018-11-27 |
| 10134864 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2018-11-20 |
| 10128377 | Independent gate FinFET with backside gate contact | Terence B. Hook, Joshua M. Rubin | 2018-11-13 |
| 10128335 | Nanowire semiconductor device including lateral-etch barrier region | Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2018-11-13 |
| 10128347 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo Vega | 2018-11-13 |