Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8187897 | Fabricating product chips and die with a feature pattern that contains information relating to the product chip | Mark J. Flemming, John C. Malinowski, Karl V. Swanke | 2012-05-29 |
| 7961932 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez +2 more | 2011-06-14 |
| 7895545 | Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning | Leah Pastel, Gustavo E. Tellez | 2011-02-22 |
| 7669159 | IC tiling pattern method, IC so formed and analysis method | Robert J. Allen, Peter A. Habitz, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski | 2010-02-23 |
| 7669170 | Circuit layout methodology using via shape process | Jason D. Hibbeler, Anthony K. Stamper, Jed H. Rankin | 2010-02-23 |
| 7657859 | Method for IC wiring yield optimization, including wire widening during and after routing | Jason D. Hibbeler, Gustavo E. Tellez | 2010-02-02 |
| 7644327 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA | Christopher B. Reynolds, Sebastian T. Ventrone, Paul S. Zuchowski | 2010-01-05 |
| 7620931 | Method of adding fabrication monitors to integrated circuit chips | James W. Adkisson, Greg Bazan, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett | 2009-11-17 |
| 7558999 | Learning based logic diagnosis | James W. Adkisson, Leendert M. Huisman, Maroun Kassab, Leah Pfeifer Pastel, David E. Sweenor | 2009-07-07 |
| 7536664 | Physical design system and method | James A. Culp, Ulrich A. Finkler, Fook-Luen Heng, Mark A. Lavin, Jin-Fuw Lee +6 more | 2009-05-19 |
| 7503021 | Integrated circuit diagnosing method, system, and program product | Matt Boucher, Richard Dauphin, Mark E. Masters, Judith H. McCullen, Sarah C. Braasch +1 more | 2009-03-10 |
| 7469395 | Wiring optimizations for power | Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic, Jagannathan Narasimhan +2 more | 2008-12-23 |
| 7373567 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA | Christopher B. Reynolds, Sebastian T. Ventrone, Paul S. Zuchowski | 2008-05-13 |
| 7346875 | Wiring optimizations for power | Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic, Jagannathan Narasimhan +2 more | 2008-03-18 |
| 7323278 | Method of adding fabrication monitors to integrated circuit chips | James W. Adkisson, Greg Bazan, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett | 2008-01-29 |
| 7308669 | Use of redundant routes to increase the yield and reliability of a VLSI layout | Markus Buehler, David J. Hathaway, Jason D. Hibbeler, Juergen Koehl | 2007-12-11 |
| 7289659 | Method and apparatus for manufacturing diamond shaped chips | Robert J. Allen, Scott Whitney Gould, Peter A. Habitz, Juergen Koehl, Gustavo E. Tellez +2 more | 2007-10-30 |
| 7285860 | Method and structure for defect monitoring of semiconductor devices using power bus wiring grids | Leah Pastel, Thomas G. Sopchak, David P. Vallett | 2007-10-23 |
| 7240322 | Method of adding fabrication monitors to integrated circuit chips | James W. Adkisson, Greg Bazan, Matthew S. Grady, Thomas G. Sopchak, David P. Vallett | 2007-07-03 |
| 7239167 | Utilizing clock shield as defect monitor | Leah Pastel, Thomas G. Sopchak, David P. Vallett | 2007-07-03 |
| 7222248 | Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range | Rafael Blanco, Kenneth J. Goodnow, Douglas W. Stout, Sebastian T. Ventrone | 2007-05-22 |
| 7194706 | Designing scan chains with specific parameter sensitivities to identify process defects | James W. Adkisson, Greg Bazan, Matthew S. Grady, Leendert M. Huisman, Mark D. Jaffe +5 more | 2007-03-20 |
| 7188322 | Circuit layout methodology using a shape processing application | Jason D. Hibbeler, Anthony K. Stamper, Jed H. Rankin | 2007-03-06 |
| 7135907 | Clock signal distribution utilizing differential sinusoidal signal pair | Anthony R. Bonaccio, Alvar A. Dean, Amir Farrahi, David J. Hathaway, Sebastian T. Ventrone | 2006-11-14 |
| 7107469 | Power down processing islands | Rafael Blanco, Kenneth J. Goodnow, Douglas W. Stout, Sebastian T. Ventrone | 2006-09-12 |