CR

Christopher B. Reynolds

IBM: 15 patents #7,450 of 70,183Top 15%
Overall (All Time): #324,607 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8381161 Method for providing a secure “gray box” view proprietary IP William R. Andersen, Oded Katz, Rina Kipnis, Lansing D. Pickup, Joseph H. Underwood 2013-02-19
8174329 Power management architecture and method of modulating oscillator frequency based on voltage supply Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams 2012-05-08
7937560 Processor pipeline architecture logic state retention systems and methods Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams 2011-05-03
7882334 Processor pipeline architecture logic state retention systems and methods Kerry Bernstein, Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Keith R. Williams 2011-02-01
7793251 Method for increasing the manufacturing yield of programmable logic devices Kenneth J. Goodnow, Clarence R. Ogilvie, Sebastian T. Ventrone, Paul S. Zuchowski 2010-09-07
7750670 System and method for dynamically executing a function in a programmable logic array Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone 2010-07-06
7644327 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA John M. Cohn, Sebastian T. Ventrone, Paul S. Zuchowski 2010-01-05
7512813 Method for system level protection of field programmable logic devices Kenneth J. Goodnow, Clarence R. Ogilvie 2009-03-31
7489163 FPGA powerup to known functional state Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone, Keith R. Williams 2009-02-10
7417453 System and method for dynamically executing a function in a programmable logic array Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone 2008-08-26
7373567 System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA John M. Cohn, Sebastian T. Ventrone, Paul S. Zuchowski 2008-05-13
7304493 FPGA powerup to known functional state Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone, Keith R. Williams 2007-12-04
7282949 FPGA powerup to known functional state Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone, Keith R. Williams 2007-10-16
7105385 FPGA blocks with adjustable porosity pass thru Sebastian T. Ventrone, Angela Weil 2006-09-12
6954085 System and method for dynamically executing a function in a programmable logic array Kenneth J. Goodnow, Clarence R. Ogilvie, Jack R. Smith, Sebastian T. Ventrone 2005-10-11