Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7095063 | Multiple supply gate array backfill structure | Kevin Grosselfinger, William F. Smith, Paul S. Zuchowski | 2006-08-22 |
| 7093213 | Method for designing an integrated circuit defect monitor | Leah Pastel | 2006-08-15 |
| 7088124 | Utilizing clock shield as defect monitor | Leah Pastel, Thomas G. Sopchak, David P. Vallett | 2006-08-08 |
| 7089514 | Defect diagnosis for semiconductor integrated circuits | James W. Adkisson, Greg Bazan, Francis Gravel, Leendert M. Huisman, Phillip J. Nigh +4 more | 2006-08-08 |
| 7078248 | Method and structure for defect monitoring of semiconductor devices using power bus wiring grids | Leah Pastel, Thomas G. Sopchak, David P. Vallett | 2006-07-18 |
| 7071757 | Clock signal distribution utilizing differential sinusoidal signal pair | Anthony R. Bonaccio, Alvar A. Dean, Amir Farrahi, David J. Hathaway, Sebastian T. Ventrone | 2006-07-04 |
| 7005874 | Utilizing clock shield as defect monitor | Leah Pastel, Thomas G. Sopchak, David P. Vallett | 2006-02-28 |
| 6998866 | Circuit and method for monitoring defects | Greg Bazan, Matthew S. Grady, Phillip J. Nigh, Leah Pastel, Thomas G. Sopchak | 2006-02-14 |
| 6985004 | Wiring optimizations for power | Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic, Jagannathan Narasimhan +2 more | 2006-01-10 |
| 6948146 | Simplified tiling pattern method | Robert J. Allen, Peter A. Habitz, William C. Leipold, Ivan L. Wemple, Paul S. Zuchowski | 2005-09-20 |
| 6924661 | Power switch circuit sizing technique | Patrick H. Buffet, Kevin Grosselfinger, Susan K. Lichtensteiger, William F. Smith | 2005-08-02 |
| 6832361 | System and method for analyzing power distribution using static timing analysis | Scott Whitney Gould, Ronald D. Rose, Ivan L. Wemple, Paul S. Zuchowski | 2004-12-14 |
| 6825711 | Power reduction by stage in integrated circuit | Kenneth J. Goodnow, Scott Whitney Gould, Douglas W. Stout, Sebastian T. Ventrone | 2004-11-30 |
| 6792582 | Concurrent logical and physical construction of voltage islands for mixed supply voltage designs | Alvar A. Dean, David J. Hathaway, David E. Lackey, Thomas Lepsic, Susan K. Lichtensteiger +2 more | 2004-09-14 |
| 6751744 | Method of integrated circuit design checking using progressive individual network analysis | Robert J. Allen, David J. Hathaway | 2004-06-15 |
| 6711719 | Method and apparatus for reducing power consumption in VLSI circuit designs | Alvar A. Dean, Amir Farrahi, David J. Hathaway, Thomas Lepsic, Patrick E. Perry +2 more | 2004-03-23 |
| 6687883 | System and method for inserting leakage reduction control in logic circuits | Alvar A. Dean, David J. Hathaway, Sebastian T. Ventrone | 2004-02-03 |
| 6651230 | Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design | Jose L. Neves, Paul S. Zuchowski | 2003-11-18 |
| 6574779 | Hierarchical layout method for integrated circuits | Robert J. Allen, Steve Lovejoy | 2003-06-03 |
| 6523154 | Method for supply voltage drop analysis during placement phase of chip design | James Venuto, Ivan L. Wemple, Paul S. Zuchowski | 2003-02-18 |
| 6523159 | Method for adding decoupling capacitance during integrated circuit design | Kerry Bernstein, Jose L. Neves | 2003-02-18 |
| 6490708 | Method of integrated circuit design by selection of noise tolerant gates | Scott Whitney Gould, Peter A. Habitz, Jose L. Neves, William F. Smith, Larry Wissel +1 more | 2002-12-03 |
| 6479974 | Stacked voltage rails for low-voltage DC distribution | Alvar A. Dean, David J. Hathaway, Patrick E. Perry, Sebastian T. Ventrone | 2002-11-12 |
| 6473881 | Pattern-matching for transistor level netlists | Valerie D. Lehner, Ulrich A. Finkler | 2002-10-29 |
| 6430733 | Contextual based groundrule compensation method of mask data set generation | Daniel C. Cole | 2002-08-06 |