Issued Patents All Time
Showing 26–50 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9009638 | Estimating transistor characteristics and tolerances for compact modeling | Terence B. Hook | 2015-04-14 |
| 8987078 | Metal semiconductor alloy contact with low resistance | Jian-Shen Yu, Zhengwen Li, Chengwen Pei, Michael Hargrove | 2015-03-24 |
| 8927378 | Trench silicide contact with low interface resistance | Chengwen Pei, Zhengwen Li, Jian-Shen Yu | 2015-01-06 |
| 8921939 | Stressed channel FET with source/drain buffers | Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus, Kai Xiu | 2014-12-30 |
| 8872281 | Silicided trench contact to buried conductive layer | Douglas D. Coolbaugh, Peter J. Lindgren, Xuefeng Lie, James S. Nakos, Bradley A. Omer +2 more | 2014-10-28 |
| 8835994 | Reduced corner leakage in SOI structure and method | Joseph Ervin, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang | 2014-09-16 |
| 8816401 | Heterojunction bipolar transistor | Renata Camillo-Castillo | 2014-08-26 |
| 8809967 | Device structures compatible with fin-type field-effect transistor technologies | Robert J. Gauthier, Jr., Junjun Li | 2014-08-19 |
| 8809953 | FET structures with trench implantation to improve back channel leakage and body resistance | David M. Fried, Kevin McStay, Paul C. Parries, Chengwen Pei, Gan Wang +2 more | 2014-08-19 |
| 8796771 | Creating anisotropically diffused junctions in field effect transistor devices | Brian J. Greene, Qingqing Liang, Edward P. Maciejewski | 2014-08-05 |
| 8759194 | Device structures compatible with fin-type field-effect transistor technologies | Robert J. Gauthier, Jr., Junjun Li | 2014-06-24 |
| 8741780 | Reduced corner leakage in SOI structure and method | Joseph Ervin, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang | 2014-06-03 |
| 8741725 | Butted SOI junction isolation structures and devices and method of fabrication | Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus, Robert R. Robison | 2014-06-03 |
| 8716759 | Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device | Matthew J. Breitwisch, Roger W. Cheek, Chung H. Lam, Beth Ann Rainey, Michael J. Zierak | 2014-05-06 |
| 8642424 | Replacement metal gate structure and methods of manufacture | Sameer H. Jain, Ying Li, Hasan M. Nayfeh, Ravikumar Ramachandran | 2014-02-04 |
| 8637871 | Asymmetric hetero-structure FET and method of manufacture | Brent A. Anderson, Edward J. Nowak, Robert R. Robison | 2014-01-28 |
| 8633096 | Creating anisotropically diffused junctions in field effect transistor devices | Brian J. Greene, Qingqing Liang, Edward P. Maciejewski | 2014-01-21 |
| 8592293 | Schottky barrier diodes for millimeter wave SiGe BiCMOS applications | Xuefeng Liu, Bradley A. Orner, Robert M. Rassel | 2013-11-26 |
| 8569810 | Metal semiconductor alloy contact with low resistance | Jian-Shen Yu, Zhengwen Li, Chengwen Pei, Michael Hargrove | 2013-10-29 |
| 8536649 | Method to reduce threshold voltage variability with through gate well implant | Geng Wang, Joseph Ervin, Paul C. Parries | 2013-09-17 |
| 8492843 | Lateral hyperabrupt junction varactor diode in an SOI substrate | Alvin J. Joseph, Robert M. Rassel, Yun Shi | 2013-07-23 |
| 8407656 | Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range | Terence B. Hook | 2013-03-26 |
| 8395217 | Isolation in CMOSFET devices utilizing buried air bags | Kangguo Cheng, Joseph Ervin, Pranita Kulkarni, Kevin McStay, Paul C. Parries +3 more | 2013-03-12 |
| 8361847 | Stressed channel FET with source/drain buffers | Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus, Kai Xiu | 2013-01-29 |
| 8338265 | Silicided trench contact to buried conductive layer | Douglas D. Coolbaugh, Peter J. Lindgren, Xuefeng Liu, James S. Nakos, Bradley A. Orner +2 more | 2012-12-25 |