Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8921939 | Stressed channel FET with source/drain buffers | Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus | 2014-12-30 |
| 8361847 | Stressed channel FET with source/drain buffers | Jeffrey B. Johnson, Ramachandran Muralidhar, Philip J. Oldiges, Viorel Ontalus | 2013-01-29 |
| 8089160 | IC interconnect for high current | Ping-Chuan Wang, Kimball M. Watson | 2012-01-03 |
| 7977712 | Asymmetric source and drain field effect structure | Huilong Zhu, Hong Lin, Katherine L. Saenger, Haizhou Yin | 2011-07-12 |
| 7525162 | Orientation-optimized PFETS in CMOS devices employing dual stress liners | Haizhou Yin, Katherine L. Saenger, Chun-Yung Sung | 2009-04-28 |
| 7436044 | Electrical fuses comprising thin film transistors (TFTS), and methods for programming same | Babar A. Khan, Chandrasekharan Kothandaraman | 2008-10-14 |
| 7375371 | Structure and method for thermally stressing or testing a semiconductor device | Giuseppe La Rosa, Kevin Kolvenbach, John G. Massey, Ping-Chuan Wang | 2008-05-20 |
| 7342294 | SOI bipolar transistors with reduced self heating | Qiqing C. Ouyang | 2008-03-11 |