Issued Patents All Time
Showing 151–165 of 165 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773700 | Aligning conductive vias with trenches | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more | 2017-09-26 |
| 9711455 | Method of forming an air gap semiconductor structure with selective cap bilayer | Stephen M. Gates, Elbert E. Huang, Dimitri Kioussis, Deepika Priyadarshini | 2017-07-18 |
| 9685366 | Forming chamferless vias using thermally decomposable porefiller | Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Michael Rizzolo | 2017-06-20 |
| 9666529 | Method and structure to reduce the electric field in semiconductor wiring interconnects | Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Theodorus E. Standaert | 2017-05-30 |
| 9666528 | BEOL vertical fuse formed over air gap | Marc A. Bergendahl, James J. Demarest, Christopher J. Waskiewicz | 2017-05-30 |
| 9607943 | Capacitors | Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang | 2017-03-28 |
| 9607886 | Self aligned conductive lines with relaxed overlay | Sean D. Burns, Lawrence A. Clevenger, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot +2 more | 2017-03-28 |
| 9553019 | Airgap protection layer for via alignment | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2017-01-24 |
| 9449871 | Hybrid airgap structure with oxide liner | Marc A. Bergendahl, James J. Demarest, Christopher J. Waskiewicz | 2016-09-20 |
| 9379057 | Method and structure to reduce the electric field in semiconductor wiring interconnects | Elbert E. Huang, Takeshi Nogami, Raghuveer R. Patlolla, Theodorus E. Standaert | 2016-06-28 |
| 9349687 | Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect | Stephen M. Gates, Elbert E. Huang, Joe Lee, Son V. Nguyen, Brown C. Peethala +1 more | 2016-05-24 |
| 9305836 | Air gap semiconductor structure with selective cap bilayer | Stephen M. Gates, Elbert E. Huang, Dimitri Kioussis, Deepika Priyadarshini | 2016-04-05 |
| 9105641 | Profile control in interconnect structures | Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III +4 more | 2015-08-11 |
| 8835305 | Method of fabricating a profile control in interconnect structures | Chih-Chao Yang, Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak +4 more | 2014-09-16 |
| 7544609 | Method for integrating liner formation in back end of line processing | Matthew S. Angyal, Habib Hichri, David Watts | 2009-06-09 |