Issued Patents All Time
Showing 51–75 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10236218 | Methods, apparatus and system for forming wrap-around contact with dual silicide | Ruilong Xie, Julien Frougier, Hiroaki Niimi, Nigel G. Cave | 2019-03-19 |
| 10229999 | Methods of forming upper source/drain regions on a vertical transistor device | John H. Zhang, Haigou Huang, Jiehui Shu | 2019-03-12 |
| 10224418 | Integrated circuit fabrication with boron etch-stop layer | Chengwen Pei, Ziyan Xu | 2019-03-05 |
| 10224330 | Self-aligned junction structures | Jianwei Peng | 2019-03-05 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10211317 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Jianwei Peng, Sipeng Gu, Hsien-Ching Lo | 2019-02-19 |
| 10204991 | Transistor structures and fabrication methods thereof | Jin Ping Liu, Min-hwa Chi | 2019-02-12 |
| 10181468 | Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming | Ziyan Xu, Chengwen Pei | 2019-01-15 |
| 10176995 | Methods, apparatus and system for gate cut process using a stress material in a finFET device | Haigou Huang | 2019-01-08 |
| 10121788 | Fin-type field effect transistors with single-diffusion breaks and method | Haiting Wang, Wei Zhao, Hong Yu, Hui Zang, Zhenyu Hu | 2018-11-06 |
| 10068810 | Multiple Fin heights with dielectric isolation | Yi Qi, Jianwei Peng, Hsien-Ching Lo, Sipeng Gu | 2018-09-04 |
| 10062772 | Preventing bridge formation between replacement gate and source/drain region through STI structure | Haigou Huang, Xintuo Dai | 2018-08-28 |
| 10050125 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Hui Zang, Hsien-Ching Lo | 2018-08-14 |
| 10032910 | FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same | Changyong Xiao, Min-hwa Chi | 2018-07-24 |
| 10026818 | Field effect transistor structure with recessed interlayer dielectric and method | Sipeng Gu, Wenhe Lin, Jeffrey Chee | 2018-07-17 |
| 10014409 | Method and structure to provide integrated long channel vertical FinFET device | David Paul Brunco | 2018-07-03 |
| 10008576 | Epi facet height uniformity improvement for FDSOI technologies | George R. Mulfinger | 2018-06-26 |
| 10002827 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Guoxiang Ning, Yuping Ren, Chin Teong Lim, Paul Ackmann | 2018-06-19 |
| 9991361 | Methods for performing a gate cut last scheme for FinFET semiconductor devices | Xintuo Dai, Haigou Huang | 2018-06-05 |
| 9972621 | Fin structure in sublitho dimension for high performance CMOS application | Chengwen Pei, Ziyan Xu | 2018-05-15 |
| 9972495 | Low-K dielectric spacer for a gate cut | — | 2018-05-15 |
| 9964605 | Methods for crossed-fins FinFET device for sensing and measuring magnetic fields | Min-hwa Chi | 2018-05-08 |
| 9935104 | Fin-type field effect transistors with single-diffusion breaks and method | Haiting Wang, Wei Zhao, Hong Yu, Hui Zang, Zhenyu Hu | 2018-04-03 |
| 9916982 | Dielectric preservation in a replacement gate process | Haigou Huang, John H. Zhang | 2018-03-13 |
| 9870942 | Method of forming mandrel and non-mandrel metal lines having variable widths | Ziyan Xu, Chengwen Pei | 2018-01-16 |