Issued Patents All Time
Showing 76–100 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9865681 | Nanowire transistors having multiple threshold voltages | John H. Zhang, Jiehui Shu | 2018-01-09 |
| 9842913 | Integrated circuit fabrication with boron etch-stop layer | Chengwen Pei, Ziyan Xu | 2017-12-12 |
| 9837553 | Vertical field effect transistor | John H. Zhang, Haigou Huang | 2017-12-05 |
| 9812365 | Methods of cutting gate structures on transistor devices | John H. Zhang, Haigou Huang, Ruilong Xie, Stan Tsai | 2017-11-07 |
| 9793358 | Non-planar semiconductor device with multiple-head epitaxial structure on fin | Xiang Hu, Changyong Xiao, Wanxun He | 2017-10-17 |
| 9761594 | Hardmask for a halo/extension implant of a static random access memory (SRAM) layout | Bingwu Liu, Randy W. Mann | 2017-09-12 |
| 9761480 | Methods of forming field effect transistor (FET) and non-FET circuit elements on a semiconductor-on-insulator substrate | Hui Zang | 2017-09-12 |
| 9761691 | Integrated circuits including replacement gate structures and methods for fabricating the same | Dong-Woon Shin, Min-hwa Chi | 2017-09-12 |
| 9761491 | Self-aligned deep contact for vertical FET | Haigou Huang, John H. Zhang | 2017-09-12 |
| 9721949 | Method of forming super steep retrograde wells on FinFET | Qizhi Liu, David L. Harame, Renata Camillo-Castillo | 2017-08-01 |
| 9704971 | Epi facet height uniformity improvement for FDSOI technologies | George R. Mulfinger | 2017-07-11 |
| 9679985 | Devices and methods of improving device performance through gate cut last process | Haigou Huang | 2017-06-13 |
| 9672313 | Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device | Guoxiang Ning, Yuping Ren, Chin Teong Lim, Paul Ackmann | 2017-06-06 |
| 9647073 | Transistor structures and fabrication methods thereof | Jin Ping Liu, Min-hwa Chi | 2017-05-09 |
| 9607989 | Forming self-aligned NiSi placement with improved performance and yield | Yue Hu, Xin-Yong WANG, Yong Meng Lee, Wen-Pin Peng, Lun Zhao +1 more | 2017-03-28 |
| 9601392 | Device characterization by time dependent charging dynamics | Ming Lei, Byoung-Gi Min | 2017-03-21 |
| 9583625 | Fin structures and multi-Vt scheme based on tapered fin and method to form | Min-hwa Chi, Edmund K. Banghart | 2017-02-28 |
| 9576894 | Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same | Sunil Kumar Singh, Ravi Prakash Srivastava, Akshey Sehgal, Teck Jung Tang | 2017-02-21 |
| 9564375 | Structures and methods for extraction of device channel width | Randy W. Mann, Sandeep Puri, Sonia Ghosh, Anuj Gupta | 2017-02-07 |
| 9548318 | Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices | Min-hwa Chi | 2017-01-17 |
| 9543297 | Fin-FET replacement metal gate structure and method of manufacturing the same | Konstantin G. Korablev, Shesh Mani Pandey, Manfred Eller | 2017-01-10 |
| 9508794 | Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads | Changyong Xiao, Xiang Hu, Wanxun He | 2016-11-29 |
| 9496280 | Semiconductor structure having logic region and analog region | Hui Zang, Bingwu Liu | 2016-11-15 |
| 9490174 | Fabricating raised fins using ancillary fin structures | Jianwei Peng, Min-hwa Chi | 2016-11-08 |
| 9484417 | Methods of forming doped transition regions of transistor structures | Manfred Eller | 2016-11-01 |