Issued Patents All Time
Showing 76–100 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9343406 | Device having self-repair Cu barrier for solving barrier degradation due to Ru CMP | Kunaljeet Tanwar | 2016-05-17 |
| 9318436 | Copper based nitride liner passivation layers for conductive copper structures | Larry Zhao, Ming He, Sean Xuan Lin, John A. Iacoponi, Errol Todd Ryan | 2016-04-19 |
| 9299745 | Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same | Sean Xuan Lin, Kunaljeet Tanwar | 2016-03-29 |
| 9297775 | Combinatorial screening of metallic diffusion barriers | Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram +3 more | 2016-03-29 |
| 9287213 | Integrated circuits with improved contact structures | Xuan Lin, Vimal Kamineni | 2016-03-15 |
| 9275874 | Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal | Kunaljeet Tanwar, Donald F. Canaperi, Raghuveer R. Patlolla | 2016-03-01 |
| 9269615 | Multi-layer barrier layer for interconnect structure | Vivian W. Ryan, Paul R. Besser | 2016-02-23 |
| 9263327 | Minimizing void formation in semiconductor vias and trenches | Sean Xuan Lin | 2016-02-16 |
| 9236557 | Magnetic tunnel junction between metal layers of a semiconductor device | Ruilong Xie, Xiuyu Cai, Hyun-Jin Cho | 2016-01-12 |
| 9236299 | Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device | Hoon Kim, Christian Witt, Larry Zhao | 2016-01-12 |
| 9209135 | Method for reducing wettability of interconnect material at corner interface and device incorporating same | Hoon Kim, Vivian W. Ryan | 2015-12-08 |
| 9190486 | Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance | Ruilong Xie, Xiuyu Cai | 2015-11-17 |
| 9190323 | Semiconductor devices with copper interconnects and methods for fabricating same | Hoon Kim | 2015-11-17 |
| 9190260 | Topological method to build self-aligned MTJ without a mask | Ruilong Xie, Xiuyu Cai, Seowoo Nam, Hyun-Jin Cho | 2015-11-17 |
| 9177858 | Methods for fabricating integrated circuits including barrier layers for interconnect structures | Tibor Bolom, Kun Ho Ahn, Bernd Hintze, Frank Koschinsky | 2015-11-03 |
| 9159610 | Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same | Moosung Chae, Larry Zhao | 2015-10-13 |
| 9159617 | Structure and method of forming silicide on fins | Xiuyu Cai | 2015-10-13 |
| 9093401 | Achieving greater planarity between upper surfaces of a layer and a conductive structure residing therein | Xiuyu Cai | 2015-07-28 |
| 9087881 | Electroless fill of trench in semiconductor structure | Sean Xuan Lin, Ming He, Larry Zhao, John A. Iacoponi, Kunaljeet Tanwar | 2015-07-21 |
| 9076792 | Multi-layer barrier layer stacks for interconnect structures | Vivian W. Ryan, Paul R. Besser | 2015-07-07 |
| 9076816 | Method and device for self-aligned contact on a non-recessed metal gate | Xiuyu Cai, Hoon Kim | 2015-07-07 |
| 9076846 | Methods for fabricating integrated circuits using surface modification to selectively inhibit etching | Errol Todd Ryan, Kunaljeet Tanwar | 2015-07-07 |
| 9064948 | Methods of forming a semiconductor device with low-k spacers and the resulting device | Xiuyu Cai, Ruilong Xie | 2015-06-23 |
| 9059255 | Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product | Vivian W. Ryan | 2015-06-16 |
| 9054052 | Methods for integration of pore stuffing material | Nicholas V. LiCausi, Errol Todd Ryan, Ming He, Moosung Chae, Kunaljeet Tanwar +4 more | 2015-06-09 |