Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9362283 | Gate structures for transistor devices for CMOS applications and products | Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty +6 more | 2016-06-07 |
| 9297775 | Combinatorial screening of metallic diffusion barriers | Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Karthik Ramani +3 more | 2016-03-29 |
| 9105497 | Methods of forming gate structures for transistor devices for CMOS applications | Zhendong Hong, Susie Tzeng, Amol Joshi, Ashish Bodke, Divya Pisharoty +6 more | 2015-08-11 |
| 8987119 | Pillar devices and methods of making thereof | Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan +1 more | 2015-03-24 |
| 8859431 | Process to remove Ni and Pt residues for NiPtSi application using chlorine gas | Anh Duong, John Foster, Olov Karlsson, James Mavrinac | 2014-10-14 |
| 8854067 | Circular transmission line methods compatible with combinatorial processing of semiconductors | Amol Joshi, Charlene Chen, John Foster, Zhendong Hong, Olov Karlsson +5 more | 2014-10-07 |
| 8759176 | Patterning of submicron pillars in a memory array | Michael Konevecki | 2014-06-24 |
| 8735302 | High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction | Amol Joshi, John Foster, Zhendong Hong, Olov Karlsson, Bei Li | 2014-05-27 |
| 8722518 | Methods for protecting patterned features during trench etch | Steven J. Radigan, Samuel V. Dunton, Michael Konevecki | 2014-05-13 |
| 8466058 | Process to remove Ni and Pt residues for NiPtSi applications using chlorine gas | Anh Duong, John Foster, Olov Karlsson, James Mavrinac | 2013-06-18 |
| 8298931 | Dual damascene with amorphous carbon for 3D deep via/trench application | Michael Konevecki | 2012-10-30 |
| 8268678 | Diode array and method of making thereof | Steven Maxwell, Michael Konevecki, Mark Clark | 2012-09-18 |
| 8163593 | Method of making a nonvolatile phase change memory cell having a reduced contact area | S. Brad Herner | 2012-04-24 |
| 8084366 | Modified DARC stack for resist patterning | Michael Chan | 2011-12-27 |
| 8071475 | Liner for tungsten/silicon dioxide interface in memory | Yoichiro Tanaka, Steven J. Radigan | 2011-12-06 |
| 8008187 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface | Samuel V. Dunton, Christopher J. Petti | 2011-08-30 |
| 7955515 | Method of plasma etching transition metal oxides | Michael Konevecki | 2011-06-07 |
| 7915163 | Method for forming doped polysilicon via connecting polysilicon layers | Michael Konevecki, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar | 2011-03-29 |
| 7915164 | Method for forming doped polysilicon via connecting polysilicon layers | Michael Konevecki, Maitreyee Mahajani, Sucheta Nallamothu, Andrew J. Walker, Tanmay Kumar | 2011-03-29 |
| 7906392 | Pillar devices and methods of making thereof | Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan +1 more | 2011-03-15 |
| 7846782 | Diode array and method of making thereof | Steven Maxwell, Michael Konevecki, Mark Clark | 2010-12-07 |
| 7790607 | Method for reducing dielectric overetch using a dielectric etch stop at a planar surface | Samuel V. Dunton, Christopher J. Petti | 2010-09-07 |
| 7728318 | Nonvolatile phase change memory cell having a reduced contact area | S. Brad Herner | 2010-06-01 |
| 7575984 | Conductive hard mask to protect patterned features during trench etch | Steven J. Radigan, Samuel V. Dunton, Michael Konevecki | 2009-08-18 |
| 7566974 | Doped polysilicon via connecting polysilicon layers | Michael Konevecki, Maitreyee Mahajani, Tanmay Kumar, Sucheta Nallamothu, Andrew J. Walker | 2009-07-28 |