Issued Patents All Time
Showing 51–75 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9859217 | Middle of the line (MOL) metal contacts | Chengyu Niu, Vimal Kamineni, Mark V. Raymond | 2018-01-02 |
| 9859120 | Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines | Lei Sun, Ruilong Xie, Ryan Ryoung-Han Kim | 2018-01-02 |
| 9853110 | Method of forming a gate contact structure for a semiconductor device | Ruilong Xie, Sean Xuan Lin | 2017-12-26 |
| 9837268 | Raised fin structures and methods of fabrication | Yi Qi, Catherine B. Labelle | 2017-12-05 |
| 9831124 | Interconnect structures | Frank W. Mont | 2017-11-28 |
| 9831174 | Devices and methods of forming low resistivity noble metal interconnect | Frank W. Mont, Errol Todd Ryan | 2017-11-28 |
| 9824921 | Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps | Andre P. Labonte, Ruilong Xie | 2017-11-21 |
| 9824970 | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures | Ruilong Xie | 2017-11-21 |
| 9805972 | Skip via structures | Sean Xuan Lin, James Jay McMahon, Shao Beng Law | 2017-10-31 |
| 9799555 | Cobalt interconnects covered by a metal cap | Frank W. Mont | 2017-10-24 |
| 9799559 | Methods employing sacrificial barrier layer for protection of vias during trench formation | Shariq Siddiqui, Frank W. Mont, Brown C. Peethala, Douglas M. Trickett | 2017-10-24 |
| 9721889 | Middle of the line (MOL) metal contacts | Chengyu Niu, Vimal Kamineni, Mark V. Raymond | 2017-08-01 |
| 9666791 | Topological method to build self-aligned MTJ without a mask | Ruilong Xie, Xiuyu Cai, Seowoo Nam, Hyun-Jin Cho | 2017-05-30 |
| 9613906 | Integrated circuits including modified liners and methods for fabricating the same | Errol Todd Ryan | 2017-04-04 |
| 9589836 | Methods of forming ruthenium conductive structures in a metallization layer | Hoon Kim | 2017-03-07 |
| 9570394 | Formation of IC structure with pair of unitary metal fins | Nicholas V. LiCausi, Errol Todd Ryan | 2017-02-14 |
| 9559059 | Methods of forming an improved via to contact interface by selective formation of a conductive capping layer | Tibor Bolom, Errol Todd Ryan | 2017-01-31 |
| 9553017 | Methods for fabricating integrated circuits including back-end-of-the-line interconnect structures | — | 2017-01-24 |
| 9530691 | Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias | Errol Todd Ryan | 2016-12-27 |
| 9466530 | Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer | Tibor Bolom, Errol Todd Ryan | 2016-10-11 |
| 9437711 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Xiuyu Cai | 2016-09-06 |
| 9425280 | Semiconductor device with low-K spacers | Xiuyu Cai, Ruilong Xie | 2016-08-23 |
| 9412660 | Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure | Ruilong Xie | 2016-08-09 |
| 9391140 | Raised fin structures and methods of fabrication | Yi Qi, Catherine B. Labelle | 2016-07-12 |
| 9373542 | Integrated circuits and methods for fabricating integrated circuits with improved contact structures | Xiuyu Cai, Hoon Kim | 2016-06-21 |