Issued Patents All Time
Showing 51–75 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6670241 | Semiconductor memory with deuterated materials | Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa +1 more | 2003-12-30 |
| 6667243 | Etch damage repair with thermal annealing | Mark T. Ramsbey, Nicholas H. Tripsas, Jeffrey A. Shields, Yider Wu | 2003-12-23 |
| 6653191 | Memory manufacturing process using bitline rapid thermal anneal | Jean Y. Yang, Amir H. Jafarpour, Tazrien Kamal, Mark T. Ramsbey, Emmanuil Lingunis +1 more | 2003-11-25 |
| 6645882 | Preparation of composite high-K/standard-K dielectrics for semiconductor devices | Joong S. Jeon, Minh Van Ngo, Robert B. Ogle | 2003-11-11 |
| 6642573 | Use of high-K dielectric material in modified ONO structure for semiconductor devices | Mark T. Ramsbey, Wei Zhang, Mark Randolph, Fred Cheung | 2003-11-04 |
| 6642066 | Integrated process for depositing layer of high-K dielectric with in-situ control of K value and thickness of high-K dielectric layer | Farzad Arsania | 2003-11-04 |
| 6633392 | X-ray reflectance system to determine suitability of SiON ARC layer | Bhanwar Singh, Ramkumar Subramanian | 2003-10-14 |
| 6620705 | Nitriding pretreatment of ONO nitride for oxide deposition | Robert B. Ogle | 2003-09-16 |
| 6617215 | Memory wordline hard mask | Tazrien Kamal, Minh Van Ngo, Mark T. Ramsbey, Jeffrey A. Shields, Jean Y. Yang +3 more | 2003-09-09 |
| 6605848 | Semiconductor device with metal gate electrode and silicon oxynitride spacer | Minh Van Ngo | 2003-08-12 |
| 6593748 | Process integration of electrical thickness measurement of gate oxide and tunnel oxides by corona discharge technique | Bhanwar Singh, Ramkumar Subramanian | 2003-07-15 |
| 6589804 | Oxide/nitride or oxide/nitride/oxide thickness measurement using scatterometry | Bhanwar Singh, Ramkumar Subramanian | 2003-07-08 |
| 6586349 | Integrated process for fabrication of graded composite dielectric material layers for semiconductor devices | Joong S. Jeon | 2003-07-01 |
| 6563578 | In-situ thickness measurement for use in semiconductor processing | Khoi A. Phan, Bhanwar Singh | 2003-05-13 |
| 6563183 | Gate array with multiple dielectric properties and method for forming same | William G. En, Minh-Ren Lin, Minh Van Ngo, Cyrus E. Tabery, Chih-Yuh Yang | 2003-05-13 |
| 6548855 | Non-volatile memory dielectric as charge pump dielectric | Mark T. Ramsbey, Kuo-Tung Chang, Nicholas H. Tripsas, Wei Zheng, Unsoon Kim | 2003-04-15 |
| 6512264 | Flash memory having pre-interpoly dielectric treatment layer and method of forming | Robert B. Ogle | 2003-01-28 |
| 6509282 | Silicon-starved PECVD method for metal gate electrode dielectric spacer | Minh Van Ngo | 2003-01-21 |
| 6500713 | Method for repairing damage to charge trapping dielectric layer from bit line implantation | Mark T. Ramsbey, Nicholas H. Tripsas | 2002-12-31 |
| 6451641 | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material | Robert B. Ogle, Joong S. Jeon, Fred Cheung, Effiong Ibok | 2002-09-17 |
| 6410388 | Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device | George Jonathan Kluth, Stephen Keetai Park, David K. Foote | 2002-06-25 |
| 6406960 | Process for fabricating an ONO structure having a silicon-rich silicon nitride layer | Dawn Hopper, David K. Foote, Bharath Rangarajan | 2002-06-18 |
| 6391730 | Process for fabricating shallow pocket regions in a non-volatile semiconductor device | George Jonathan Kluth | 2002-05-21 |
| 6376341 | Optimization of thermal cycle for the formation of pocket implants | George Jonathan Kluth | 2002-04-23 |
| 6319775 | Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device | Robert B. Ogle, Susan Kim, Kenneth Wo-Wai Au | 2001-11-20 |