Issued Patents 2021
Showing 1–25 of 85 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211291 | Via formation with robust hardmask removal | Ruilong Xie, Christopher J. Waskiewicz, Kangguo Cheng | 2021-12-28 |
| 11205592 | Self-aligned top via structure | Ruilong Xie, Cheng Chi, Kangguo Cheng | 2021-12-21 |
| 11205588 | Interconnect architecture with enhanced reliability | Baozhen Li, Naftali E. Lustig | 2021-12-21 |
| 11205591 | Top via interconnect with self-aligned barrier layer | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-12-21 |
| 11201112 | Fully-aligned skip-vias | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-12-14 |
| 11201056 | Pitch multiplication with high pattern fidelity | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-12-14 |
| 11195751 | Bilayer barrier for interconnect and memory structures formed in the BEOL | Baozhen Li | 2021-12-07 |
| 11177169 | Interconnects with gouged vias | Kenneth Chun Kuen Cheng, Koichi Motoyama, Hosadurga Shobha | 2021-11-16 |
| 11177214 | Interconnects with hybrid metal conductors | Kenneth Chun Kuen Cheng, Chanro Park, Koichi Motoyama | 2021-11-16 |
| 11177213 | Embedded small via anti-fuse device | Baozhen Li, Tianji Zhou, Ashim Dutta, Saumya Sharma | 2021-11-16 |
| 11177163 | Top via structure with enlarged contact area with upper metallization level | Koichi Motoyama, Chanro Park, Kenneth Chun Kuen Cheng | 2021-11-16 |
| 11177167 | Ultrathin multilayer metal alloy liner for nano Cu interconnects | Daniel C. Edelstein, Alfred Grill, Seth L. Knupp, Son V. Nguyen, Takeshi Nogami +2 more | 2021-11-16 |
| 11171044 | Planarization controllability for interconnect structures | Ruilong Xie, Chanro Park, Kangguo Cheng, Julien Frougier | 2021-11-09 |
| 11164878 | Interconnect and memory structures having reduced topography variation formed in the BEOL | Baozhen Li, Raghuveer R. Patlolla, Cornelius Brown Peethala | 2021-11-02 |
| 11164774 | Interconnects with spacer structure for forming air-gaps | Kenneth Chun Kuen Cheng, Koichi Motoyama, Chanro Park | 2021-11-02 |
| 11164779 | Bamboo tall via interconnect structures | Michael Rizzolo, Theodorus E. Standaert | 2021-11-02 |
| 11158584 | Selective CVD alignment-mark topography assist for non-volatile memory | Michael Rizzolo, Lawrence A. Clevenger, Benjamin D. Briggs | 2021-10-26 |
| 11158786 | MRAM device formation with controlled ion beam etch of MTJ | Ashim Dutta, Lijuan Zou, John C. Arnold | 2021-10-26 |
| 11152300 | Electrical fuse with metal line migration | Baozhen Li, Yan Li, Keith Kwong Hon Wong | 2021-10-19 |
| 11145813 | Bottom electrode for semiconductor memory device | Theodorus E. Standaert, Daniel C. Edelstein | 2021-10-12 |
| 11145591 | Integrated circuit (IC) device integral capacitor and anti-fuse | Jim Shih-Chun Liang, Baozhen Li | 2021-10-12 |
| 11139202 | Fully aligned top vias with replacement metal lines | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-10-05 |
| 11139242 | Via-to-metal tip connections in multi-layer chips | Ruilong Xie, Chi-Chun Liu, Kangguo Cheng | 2021-10-05 |
| 11133216 | Interconnect structure | Hsueh-Chung Chen, Roger A. Quon | 2021-09-28 |
| 11133457 | Controllable formation of recessed bottom electrode contact in a memory metallization stack | Raghuveer R. Patlolla, James J. Kelly | 2021-09-28 |