Issued Patents 2021
Showing 26–50 of 85 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11133216 | Interconnect structure | Hsueh-Chung Chen, Roger A. Quon | 2021-09-28 |
| 11127676 | Removal or reduction of chamfer for fully-aligned via | Chanro Park, Koichi Motoyama, Kenneth Chun Kuen Cheng | 2021-09-21 |
| 11121082 | Sub-ground rule e-Fuse structure | Andrew Tae Kim, Baozhen Li, Ernest Y. Wu | 2021-09-14 |
| 11107984 | Protuberant contacts for resistive switching devices | Takashi Ando, Lawrence A. Clevenger | 2021-08-31 |
| 11107731 | Self-aligned repaired top via | Ruilong Xie, Carl Radens, Juntao Li, Kangguo Cheng | 2021-08-31 |
| 11101175 | Tall trenches for via chamferless and self forming barrier | Yann Mignot, Hosadurga Shobha | 2021-08-24 |
| 11101213 | EFuse structure with multiple links | Baozhen Li, Jim Shih-Chun Liang, Tian Shen | 2021-08-24 |
| 11099230 | Electromigration test structures for void localization | Baozhen Li | 2021-08-24 |
| 11094580 | Structure and method to fabricate fully aligned via with reduced contact resistance | Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama | 2021-08-17 |
| 11094630 | Formation of semiconductor devices including electrically programmable fuses | Juntao Li | 2021-08-17 |
| 11094527 | Wet clean solutions to prevent pattern collapse | Cornelius Brown Peethala, Raghuveer R. Patlolla, Hsueh-Chung Chen | 2021-08-17 |
| 11087993 | Double replacement metal line patterning | Ruilong Xie, Kangguo Cheng, Hsueh-Chung Chen | 2021-08-10 |
| 11074387 | Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance | Prasad Bhosale, Michael Rizzolo | 2021-07-27 |
| 11069567 | Modulating metal interconnect surface topography | Conal E. Murray | 2021-07-20 |
| 11069611 | Liner-free and partial liner-free contact/via structures | — | 2021-07-20 |
| 11063089 | Resistive memory device with meshed electrodes | Takashi Ando, Lawrence A. Clevenger, Michael Rizzolo | 2021-07-13 |
| 11056425 | Structural enhancement of Cu nanowires | Daniel C. Edelstein | 2021-07-06 |
| 11056426 | Metallization interconnect structure formation | Yann Mignot, Hosadurga Shobha, Hsueh-Chung Chen | 2021-07-06 |
| 11037795 | Planarization of dielectric topography and stopping in dielectric | Hari Prasad Amanapu, Cornelius Brown Peethala, Iqbal Rashid Saraf, Raghuveer R. Patlolla | 2021-06-15 |
| 11035029 | Material for forming metal matrix composite and metal matrix composite bulk | Li-Shing Chou, Chi-San Chen, Chih-Jung Weng, Heng-Yi Tsai | 2021-06-15 |
| 11031339 | Metal interconnects | Raghuveer R. Patlolla, Cornelius Brown Peethala | 2021-06-08 |
| 11031542 | Contact via with pillar of alternating layers | Daniel C. Edelstein, Michael Rizzolo, Theodorus E. Standaert | 2021-06-08 |
| 11031457 | Low resistance high capacitance density MIM capacitor | Baozhen Li | 2021-06-08 |
| 11024539 | Self-aligned cut process for self-aligned via process window | Ruilong Xie, Jing Guo, Kangguo Cheng | 2021-06-01 |
| 11024577 | Embedded anti-fuses for small scale applications | Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama | 2021-06-01 |