Issued Patents 2021
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11171006 | Simultaneous plating of varying size features on semiconductor substrate | Mukta G. Farooq | 2021-11-09 |
| 11152298 | Metal via structure | Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu, Hsueh-Chung Chen, Daniel J. Vincent | 2021-10-19 |
| 11133457 | Controllable formation of recessed bottom electrode contact in a memory metallization stack | Raghuveer R. Patlolla, Chih-Chao Yang | 2021-09-28 |
| 11069564 | Double metal patterning | Hsueh-Chung Chen, Yongan Xu, Yann Mignot, Lawrence A. Clevenger | 2021-07-20 |
| 11063126 | Metal contact isolation for semiconductor structures | Su Chen Fan, Yann Mignot, Hsueh-Chung Chen | 2021-07-13 |
| 11049844 | Semiconductor wafer having trenches with varied dimensions for multi-chip modules | Ravi K. Bonam, Mukta G. Farooq, Dinesh Gupta, Kamal K. Sikka, Joshua M. Rubin | 2021-06-29 |
| 10978342 | Interconnect with self-forming wrap-all-around barrier layer | Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas Anthony Lanzillo +3 more | 2021-04-13 |
| 10971356 | Stack viabar structures | Su Chen Fan, Hsueh-Chung Chen, Yann Mignot, Terence B. Hook | 2021-04-06 |
| 10943883 | Planar wafer level fan-out of multi-chip modules having different size chips | Ravi K. Bonam, Mukta G. Farooq, Dinesh Gupta | 2021-03-09 |
| 10910307 | Back end of line metallization structure | Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang | 2021-02-02 |
| 10903116 | Void-free metallic interconnect structures with self-formed diffusion barrier layers | Joseph F. Maniscalco, Koichi Motoyama, Hosadurga Shobha, Chih-Chao Yang | 2021-01-26 |
| 10903161 | Back end of line metallization structure | Raghuveer R. Patlolla, Cornelius Brown Peethala, Chih-Chao Yang | 2021-01-26 |