Issued Patents 2018
Showing 276–300 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9905469 | Method and structure for forming FinFET CMOS with dual doped STI regions | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-02-27 |
| 9899373 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-02-20 |
| 9899515 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2018-02-20 |
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-20 |
| 9899391 | Metal trench capacitor and improved isolation and methods of manufacture | Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang | 2018-02-20 |
| 9899384 | Self aligned structure and method for high-K metal gate work function tuning | Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2018-02-20 |
| 9899383 | Forming gates with varying length using sidewall image transfer | Juntao Li, Geng Wang, Qintao Zhang | 2018-02-20 |
| 9899378 | Simultaneously fabricating a high voltage transistor and a finFET | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2018-02-20 |
| 9899372 | Forming on-chip metal-insulator-semiconductor capacitor | Zhenxing Bi, Peng Xu, Chen Zhang | 2018-02-20 |
| 9892925 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2018-02-13 |
| 9893181 | Uniform gate length in vertical field effect transistors | Peng Xu | 2018-02-13 |
| 9893169 | Fabrication of a vertical fin field effect transistor having a consistent channel width | Juntao Li | 2018-02-13 |
| 9893166 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-02-13 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9893145 | On chip MIM capacitor | Theodorus E. Standaert | 2018-02-13 |
| 9893022 | Self-destructive circuits under radiation | Qing Cao, Fei Liu | 2018-02-13 |
| 9892978 | Forming a CMOS with dual strained channels | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-02-13 |
| 9892976 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2018-02-13 |
| 9892975 | Adjacent strained <100> NFET fins and <110> PFET fins | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9892973 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Juntao Li, Chun-Chen Yeh | 2018-02-13 |
| 9892961 | Air gap spacer formation for nano-scale semiconductor devices | Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen +2 more | 2018-02-13 |
| 9892926 | Replacement low-k spacer | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie | 2018-02-13 |
| 9892910 | Method and structure for forming a dense array of single crystalline semiconductor nanocrystals | Hong He, Juntao Li | 2018-02-13 |
| 9887198 | Semiconductor devices with sidewall spacers of equal thickness | Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2018-02-06 |
| 9887197 | Structure containing first and second vertically stacked nanosheets having different crystallographic orientations | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-06 |