Issued Patents 2018
Showing 25 most recent of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163721 | Hybridization fin reveal for uniform fin reveal depth across different fin pitches | Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie | 2018-12-25 |
| 10164007 | Transistor with improved air spacer | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-12-25 |
| 10164056 | Vertical field effect transistors with uniform threshold voltage | Kangguo Cheng, Xin Miao, Heng Wu | 2018-12-25 |
| 10157745 | High aspect ratio gates | Kangguo Cheng, Sivananda K. Kanakasabapathy | 2018-12-18 |
| 10147651 | Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels | Zhenxing Bi, Kangguo Cheng, Jie Yang | 2018-12-04 |
| 10147635 | Different shallow trench isolation fill in fin and non-fin regions of finFET | Kangguo Cheng, Chen Zhang | 2018-12-04 |
| 10147808 | Techniques for forming vertical tunneling FETS | Juntao Li, Kangguo Cheng, Xin Miao | 2018-12-04 |
| 10141420 | Transistors with dielectric-isolated source and drain regions | Kangguo Cheng, Choonghyun Lee, Juntao Li | 2018-11-27 |
| 10141313 | FinFET with uniform shallow trench isolation recess | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-11-27 |
| 10141441 | Vertical transistor with back bias and reduced parasitic capacitance | Kangguo Cheng, Xin Miao, Chen Zhang | 2018-11-27 |
| 10134859 | Transistor with asymmetric spacers | Zhenxing Bi, Kangguo Cheng, Heng Wu | 2018-11-20 |
| 10134595 | High aspect ratio gates | Kangguo Cheng, Sivananda K. Kanakasabapathy | 2018-11-20 |
| 10128235 | Asymmetrical vertical transistor | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-11-13 |
| 10128238 | Integrated circuit having oxidized gate cut region and method to fabricate same | Kangguo Cheng, Andrew M. Greene | 2018-11-13 |
| 10128004 | High temperature strength, corrosion resistant, accident tolerant nuclear fuel assembly grid | Edward J. Lahoda | 2018-11-13 |
| 10115728 | Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench | Zuoguang Liu, Gen Tsutsui, Heng Wu | 2018-10-30 |
| 10103243 | Unipolar spacer formation for finFETS | Kangguo Cheng, Jie Yang | 2018-10-16 |
| 10103063 | Forming a hybrid channel nanosheet semiconductor structure | Kangguo Cheng | 2018-10-16 |
| 10096524 | Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-10-09 |
| 10096695 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-10-09 |
| 10090412 | Vertical transistor with back bias and reduced parasitic capacitance | Kangguo Cheng, Xin Miao, Chen Zhang | 2018-10-02 |
| 10084094 | Wrapped source/drain contacts with enhanced area | Kangguo Cheng, Zuoguang Liu, Heng Wu | 2018-09-25 |
| 10079287 | Gate cut device fabrication with extended height gates | Kangguo Cheng, Andrew M. Greene, John R. Sporre | 2018-09-18 |
| 10079229 | Resistor fins | Zhenxing Bi, Kangguo Cheng, Juntao Li | 2018-09-18 |
| 10068807 | Uniform shallow trench isolation | Kangguo Cheng, Junli Wang, Chen Zhang | 2018-09-04 |