PH

Pouya Hashemi

IBM: 89 patents #10 of 10,623Top 1%
Overall (2018): #62 of 503,207Top 1%
89
Patents 2018

Issued Patents 2018

Showing 25 most recent of 89 patents

Patent #TitleCo-InventorsDate
10164092 Tapered vertical FET having III-V channel Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-12-25
10158001 Heterogeneous source drain region and extension region Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2018-12-18
10147741 FinFET with stacked faceted S/D epitaxy for improved contact resistance Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-12-04
10147820 Germanium condensation for replacement metal gate devices with silicon germanium channel Takashi Ando, Choonghyun Lee 2018-12-04
10141405 Lateral bipolar junction transistor with abrupt junction and compound buried oxide Kevin K. Chan, Tak H. Ning, Alexander Reznicek 2018-11-27
10141309 Tight pitch inverter using vertical transistors Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-11-27
10141406 Tensile strained NFET and compressively strained PFET formed on strain relaxed buffer Karthik Balakrishnan, Keith E. Fogel, Alexander Reznicek 2018-11-27
10134917 Tight pitch vertical transistor EEPROM Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek 2018-11-20
10134831 Deformable and flexible capacitor Karthik Balakrishnan, Stephen W. Bedell, Alexander Reznicek 2018-11-20
10134882 Method of junction control for lateral bipolar junction transistor Kam-Leung Lee, Tak H. Ning, Jeng-Bang Yau 2018-11-20
10134833 Multiple work function device using GeOx/TiN cap on work function setting metal Takashi Ando, Choonghyun Lee 2018-11-20
10109737 Method of forming high-germanium content silicon germanium alloy fins on insulator Renee T. Mo, John A. Ott, Alexander Reznicek 2018-10-23
10090384 Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer Karthik Balakrishnan, Keith E. Fogel, Alexander Reznicek 2018-10-02
10090307 Decoupling capacitor on strain relaxation buffer layer Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-10-02
10083907 Method and structure for forming on-chip anti-fuse with reduced breakdown voltage Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2018-09-25
10083882 Nanowire semiconductor device Karthik Balakrishnan, Sanghoon Lee 2018-09-25
10084090 Method and structure of stacked FinFET Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2018-09-25
10084064 Fabrication of strained vertical p-type field effect transistors by bottom condensation Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-09-25
10083875 Vertical transistors having different gate lengths Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek 2018-09-25
10079288 Contact formation on germanium-containing substrates using hydrogenated silicon Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek 2018-09-18
10079303 Method to form strained nFET and strained pFET nanowires on a same substrate Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek 2018-09-18
10074720 Digital alloy vertical lamellae finfet with current flow in alloy layer direction Karthik Balakrishnan, Stephen W. Bedell, Bahman Hekmatshoartabari, Alexander Reznicek 2018-09-11
10069008 Vertical transistor pass gate device Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek 2018-09-04
10062643 Nickel-silicon fuse for FinFET structures Kangguo Cheng, Keith E. Fogel, Alexander Reznicek 2018-08-28
10056503 MIS capacitor for finned semiconductor structure Keith E. Fogel, Shogo Mochizuki, Alexander Reznicek 2018-08-21