Issued Patents 2018
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10164103 | Forming strained channel with germanium condensation | Kangguo Cheng, Jie Yang | 2018-12-25 |
| 10141426 | Vertical transistor device | Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang | 2018-11-27 |
| 10134763 | Gate top spacer for finFET | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2018-11-20 |
| 10128372 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-11-13 |
| 10115824 | Forming a contact for a semiconductor device | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Ruilong Xie | 2018-10-30 |
| 10103065 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2018-10-16 |
| 10096713 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Gen Tsutsui, Chun-Chen Yeh | 2018-10-09 |
| 10084082 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-09-25 |
| 10084065 | Reducing resistance of bottom source/drain in vertical channel devices | Junli Wang | 2018-09-25 |
| 10079299 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2018-09-18 |
| 10068920 | Silicon germanium fins on insulator formed by lateral recrystallization | Alexander Reznicek, Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov | 2018-09-04 |
| 10056484 | VTFET devices utilizing low temperature selective epitaxy | Hemanth Jagannathan | 2018-08-21 |
| 10056503 | MIS capacitor for finned semiconductor structure | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2018-08-21 |
| 10032912 | Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions | Pierre Morin, Kangguo Cheng, Jody A. Fronheiser, Xiuyu Cai, Juntao Li +3 more | 2018-07-24 |
| 10020384 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2018-07-10 |
| 10020303 | Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-07-10 |
| 10008417 | Vertical transport fin field effect transistors having different channel lengths | Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung | 2018-06-26 |
| 9997407 | Voidless contact metal structures | Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Alexander Reznicek | 2018-06-12 |
| 9991255 | FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-06-05 |
| 9991258 | FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-06-05 |
| 9991382 | Vertical field effect transistor with abrupt extensions at a bottom source/drain structure | Alexander Reznicek | 2018-06-05 |
| 9985114 | Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2018-05-29 |
| 9972682 | Low resistance source drain contact formation | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Chun-Chen Yeh | 2018-05-15 |
| 9966253 | Forming nanotips | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li | 2018-05-08 |
| 9960272 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-05-01 |