Issued Patents 2018
Showing 226–250 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9941378 | Air-gap top spacer and self-aligned metal gate for vertical FETs | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-04-10 |
| 9941370 | Vertical field-effect-transistors having multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-04-10 |
| 9941352 | Transistor with improved air spacer | Zhenxing Bi, Juntao Li, Peng Xu | 2018-04-10 |
| 9941205 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2018-04-10 |
| 9941150 | Method and structure for minimizing fin reveal variation in FinFET transistor | Zhenxing Bi, Juntao Li, Hao Tang | 2018-04-10 |
| 9935018 | Methods of forming vertical transistor devices with different effective gate lengths | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2018-04-03 |
| 9935181 | FinFET having highly doped source and drain regions | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2018-04-03 |
| 9935180 | Fin cut for taper device | Ruilong Xie, Tenko Yamashita | 2018-04-03 |
| 9935102 | Method and structure for improving vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2018-04-03 |
| 9935101 | Vertical field effect transistor with uniform gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2018-04-03 |
| 9935014 | Nanosheet transistors having different gate dielectric thicknesses on the same chip | Juntao Li, Geng Wang, Qintao Zhang | 2018-04-03 |
| 9929060 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2018-03-27 |
| 9929290 | Electrical and optical via connections on a same chip | Juntao Li, Chengwen Pei, Geng Wang, Joseph Ervin | 2018-03-27 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9929256 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2018-03-27 |
| 9929247 | Etch stop for airgap protection | Ruilong Xie, Tenko Yamashita | 2018-03-27 |
| 9929246 | Forming air-gap spacer for vertical field effect transistor | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-27 |
| 9929163 | Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET) | Veeraraghavan S. Basker, Ali Khakifirooz | 2018-03-27 |
| 9929145 | Bipolar transistor compatible with vertical FET fabrication | Brent A. Anderson, Terence B. Hook, Tak H. Ning | 2018-03-27 |
| 9929046 | Self-aligned contact cap | Peng Xu | 2018-03-27 |
| 9923083 | Embedded endpoint fin reveal | Peng Xu | 2018-03-20 |
| 9923160 | Method of assembling carbon nanotubes of a semiconductor device via fringing field assisted dielectrophoresis | Qing Cao, Shu-Jen Han, Zhengwen Li, Fei Liu | 2018-03-20 |
| 9922886 | Silicon-germanium FinFET device with controlled junction | Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek | 2018-03-20 |
| 9923055 | Inner spacer for nanosheet transistors | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-20 |