Issued Patents 2018
Showing 176–200 of 338 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9991328 | Tunable on-chip nanosheet resistor | Zhenxing Bi, Wei Wang, Zheng Xu | 2018-06-05 |
| 9991254 | Forming horizontal bipolar junction transistor compatible with nanosheets | Juntao Li, Geng Wang, Qintao Zhang | 2018-06-05 |
| 9991168 | Germanium dual-fin field effect transistor | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-06-05 |
| 9985030 | FinFET semiconductor device having integrated SiGe fin | Hong He, Ali Khakifirooz, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-05-29 |
| 9985024 | Minimizing shorting between FinFET epitaxial regions | Balasubramanian Pranatharthiharan, Alexander Reznicek, Charan V. Surisetty | 2018-05-29 |
| 9985021 | Shallow trench isolation recess process flow for vertical field effect transistor fabrication | Zhenxing Bi, Bruce Miao, Xin Miao | 2018-05-29 |
| 9984937 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2018-05-29 |
| 9984936 | Methods of forming an isolated nano-sheet transistor device and the resulting device | Ruilong Xie, Siva P. Adusumilli, Pietro Montanini, Robinhsinku Chao | 2018-05-29 |
| 9984893 | Fin cut for taper device | Ruilong Xie, Tenko Yamashita | 2018-05-29 |
| 9984877 | Fin patterns with varying spacing without fin cut | Marc A. Bergendahl, John R. Sporre, Sean Teehan | 2018-05-29 |
| 9985138 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Marc A. Bergendahl, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-05-29 |
| 9985135 | Replacement low-k spacer | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie | 2018-05-29 |
| 9985117 | Method and structure for forming dielectric isolated finFET with improved source/drain epitaxy | Juntao Li | 2018-05-29 |
| 9985107 | Method and structure for forming MOSFET with reduced parasitic capacitance | Peng Xu, Chen Zhang | 2018-05-29 |
| 9985097 | Integrated capacitors with nanosheet transistors | James J. Demarest, John G. Gaudiello, Juntao Li | 2018-05-29 |
| 9985096 | High thermal budget compatible punch through stop integration using doped glass | Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh | 2018-05-29 |
| 9978775 | FinFET device with abrupt junctions | Hong He, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo | 2018-05-22 |
| 9972542 | Hybrid-channel nano-sheet FETs | Zhenxing Bi, Peng Xu, Wenyu Xu | 2018-05-15 |
| 9972700 | Vertical field effect transistors with bottom source/drain epitaxy | Xin Miao, Wenyu Xu, Chen Zhang | 2018-05-15 |
| 9972620 | Preventing shorting between source and/or drain contacts and gate | Charan V. Surisetty, Dominic J. Schepis, Alexander Reznicek | 2018-05-15 |
| 9972540 | Semiconductor device having multiple thickness oxides | Qing Cao, Zhengwen Li, Fei Liu | 2018-05-15 |
| 9966374 | Semiconductor device with gate structures having low-K spacers on sidewalls and electrical contacts therebetween | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2018-05-08 |
| 9966454 | Contact area to trench silicide resistance reduction by high-resistance interface removal | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-05-08 |
| 9966430 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Xin Miao, Ruilong Xie, Tenko Yamashita | 2018-05-08 |
| 9966387 | Strain release in pFET regions | Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim | 2018-05-08 |