Issued Patents All Time
Showing 26–50 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7629275 | Multiple-time flash anneal process | Jennifer Chen, Chi-Chun Chen | 2009-12-08 |
| 7598176 | Method for photoresist stripping and treatment of low-k dielectric material | Jang-Shiang Tsai, Yi-Nien Su, Chung-Chi Ko, Jyu-Horng Shieh, Peng-Fu Hsu | 2009-10-06 |
| 7579248 | Resolving pattern-loading issues of SiGe stressor | Yu-Lien Huang, Jim Huang, Ling-Yen Yeh | 2009-08-25 |
| 7531399 | Semiconductor devices and methods with bilayer dielectrics | Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent Chang, Yong-Tian Hou +1 more | 2009-05-12 |
| 7465634 | Method of forming integrated circuit devices having n-MOSFET and p-MOSFET transistors with elevated and silicided source/drain structures | Peng-Soon Lim, Yong-Tian Hou, Jin Ying | 2008-12-16 |
| 7436009 | Via structures and trench structures and dual damascene structures | Yi-Chen Huang, Chien-Chung Fu, Ming-Hong Hsieh, Hui Ouyang, Yi-Nien Su | 2008-10-14 |
| 7429769 | Recessed channel field effect transistor (FET) device | Carlos H. Diaz, Yi-Ming Sheu, Syun-Ming Jang, Fu-Liang Yang | 2008-09-30 |
| 7410854 | Method of making FUSI gate and resulting structure | Liang-Gi Yao, Shih-Chang Chen, Mong-Song Liang | 2008-08-12 |
| 7402866 | Backside contacts for MOS devices | Mong-Song Liang | 2008-07-22 |
| 7400401 | Measuring low dielectric constant film properties during processing | Jang-Shiang Tsai, Peng-Fu Hsu, Baw-Ching Perng, Ju-Wang Hsu, Jyu-Horng Shieh +1 more | 2008-07-15 |
| 7390753 | In-situ plasma treatment of advanced resists in fine pattern definition | Li-Te Lin, Yui Wang, Huan-Just Lin, Yuan-Hung Chiu | 2008-06-24 |
| 7378713 | Semiconductor devices with dual-metal gate structures and fabrication methods thereof | Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin | 2008-05-27 |
| 7373941 | Wet cleaning cavitation system and method to remove particulate wafer contamination | Chun-Li Chou, Peng-Fu Hsu | 2008-05-20 |
| 7354524 | Method and system for processing multi-layer films | Hui Yang, Miao-Ju Hsu, Chao-Cheng Chen | 2008-04-08 |
| 7354847 | Method of trimming technology | Bor-Wen Chan, Yi-Chun Huang, Baw-Ching Perng | 2008-04-08 |
| 7341943 | Post etch copper cleaning using dry plasma | Chen-Nan Yeh, Miao-Ju Hsu | 2008-03-11 |
| 7307009 | Phosphoric acid free process for polysilicon gate definition | Li-Te Lin, Fang Chen, Huin-Jer Lin, Yuan-Hung Chiu | 2007-12-11 |
| 7301645 | In-situ critical dimension measurement | Shiang-Bau Wang, Yuan-Hung Chiu, Chao-Tzung Tsai | 2007-11-27 |
| 7294544 | Method of making a metal-insulator-metal capacitor in the CMOS process | Yen-Shih Ho, Jau-Yuann Chung, Chun-Hon Chen | 2007-11-13 |
| RE39913 | Method to control gate CD | Huan-Just Lin, Fang Chen | 2007-11-06 |
| 7276417 | Hybrid STI stressor with selective re-oxidation anneal | Kai-Ting Tseng, Yu-Lien Huang, Hao-Ming Lien, Ling-Yen Yeh | 2007-10-02 |
| 7271448 | Multiple gate field effect transistor structure | Ju-Wang Hsu, Jyu-Horng Shieh, Chang-Yun Chang, Zhong Tang Xuan, Sheng-Da Liu | 2007-09-18 |
| 7265060 | Bi-level resist structure and fabrication method for contact holes on semiconductor substrates | Ming-Huan Tsai, Tsang-Jiuh Wu, Ju-Wang Hsu | 2007-09-04 |
| 7265056 | Method for forming novel BARC open for precision critical dimension control | Ming-Huan Tsai, Ru-Chian Chiang | 2007-09-04 |
| 7241674 | Method of forming silicided gate structure | Bor-Wen Chan, Jyu-Horng Shieh | 2007-07-10 |