Issued Patents All Time
Showing 1–25 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10861751 | Method of semiconductor integrated circuit fabrication | De-Wei Yu, Chia Ping Lo, Weng Chang, Yee-Chia Yeo, Ziwei Fang | 2020-12-08 |
| 10483170 | Method of semiconductor integrated circuit fabrication | De-Wei Yu, Chia Ping Lo, Weng Chang, Yee-Chia Yeo, Ziwei Fang | 2019-11-19 |
| 10008418 | Method of semiconductor integrated circuit fabrication | De-Wei Yu, Chia Ping Lo, Weng Chang, Yee-Chia Yeo, Ziwei Fang | 2018-06-26 |
| 9922827 | Method of forming a semiconductor structure | Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann | 2018-03-20 |
| 9893160 | Methods of forming gate dielectric material | Chia-Cheng Chen, Clement Hsingjen Wann | 2018-02-13 |
| 9385208 | Semiconductor device having high-K gate dielectric layer | Kun-Yu Lee, Yasutoshi Okuno, Clement Hsingjen Wann | 2016-07-05 |
| 9362123 | Structure and method for integrated devices on different substartes with interfacial engineering | I-Ming Chang, Yasutoshi Okuno, Chih-Hao Chang, Shou-Zen Chang, Clement Hsingjen Wann | 2016-06-07 |
| 9257349 | Method of scavenging impurities in forming a gate stack having an interfacial layer | Kuan-Ting Liu, Yasutoshi Okuno, Clement Hsingjen Wann | 2016-02-09 |
| 9245970 | Semiconductor structure having interfacial layer and high-k dielectric layer | Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann | 2016-01-26 |
| 9194804 | Stress analysis of 3-D structures using tip-enhanced Raman scattering technology | Yasutoshi Okuno, Wei-Shan Hu, Yusuke Oniki, Ling-Yen Yeh, Clement Hsingjen Wann | 2015-11-24 |
| 9040393 | Method of forming semiconductor structure | Chia-Cheng Chen, Ta-Ming Kuan, Jeff J. Xu, Clement Hsingjen Wann | 2015-05-26 |
| 9006056 | Method for reducing interfacial layer thickness for high-k and metal gate stack | Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann | 2015-04-14 |
| 8987095 | Method of fabricating a carbon-free dielectric layer over a carbon-doped dielectric layer | Kun-Yu Lee, Yasutoshi Okuno, Clement Hsingjen Wann | 2015-03-24 |
| 8785272 | Process to make high-K transistor dielectrics | Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang | 2014-07-22 |
| 8766379 | Multi-layer scavenging metal gate stack for ultra-thin interfacial dielectric layer | Kuan-Ting Liu, Yasutoshi Okuno, Clement Hsingjen Wann | 2014-07-01 |
| 8759185 | Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same | Chih-Hao Wang, Shang-Chih Chen, Yen-Ping Wang, Hsien-Kuang Chiu, Chenming Hu | 2014-06-24 |
| 8603924 | Methods of forming gate dielectric material | Chia-Cheng Chen, Clement Hsingjen Wann | 2013-12-10 |
| 8564018 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2013-10-22 |
| 8470659 | Method for reducing interfacial layer thickness for high-k and metal gate stack | Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann | 2013-06-25 |
| 8294201 | High-k gate dielectric and method of manufacture | Chen-Hua Yu | 2012-10-23 |
| RE43673 | Dual gate dielectric scheme: SiON for high performance devices and high K for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Shih-Chang Chen | 2012-09-18 |
| 8268683 | Method for reducing interfacial layer thickness for high-K and metal gate stack | Chun-Hu Cheng, Chen-Yi Lee, Jeff J. Xu, Clement Hsingjen Wann | 2012-09-18 |
| 8115263 | Laminated silicon gate electrode | Chia-Lin Chen, Shih-Chang Chen | 2012-02-14 |
| 8106469 | Methods and apparatus of fluorine passivation | Jeff J. Xu, Ta-Ming Kuan | 2012-01-31 |
| 8097924 | Ultra-shallow junction MOSFET having a high-k gate dielectric and in-situ doped selective epitaxy source/drain extensions and a method of making same | Chih-Hao Wang, Shang-Chih Chen, Yen-Ping Wang, Hsien-Kuang Chiu, Chenming Hu | 2012-01-17 |