Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6982208 | Method for producing high throughput strained-Si channel MOSFETS | Kuen-Chyr Lee, Shih-Chang Chen, Mong-Song Liang | 2006-01-03 |
| 6936530 | Deposition method for Si-Ge epi layer on different intermediate substrates | Kuen-Chyr Lee, Shih-Chang Chen, Mong-Song Liang | 2005-08-30 |
| 6914313 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Shih-Chang Chen | 2005-07-05 |
| 6911369 | Discontinuity prevention for SiGe deposition | Kuen-Chyr Lee, Fu Chin Yang, Shih-Chang Chen, Mong-Song Liang | 2005-06-28 |
| 6890811 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Shih-Chang Chen | 2005-05-10 |
| 6878610 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2005-04-12 |
| 6861339 | Method for fabricating laminated silicon gate electrode | Chia-Lin Chen, Shih-Chang Chen | 2005-03-01 |
| 6780741 | Method of forming a novel gate electrode structure comprised of a silicon-germanium layer located between random grained polysilicon layers | Chia-Lin Chen, Shih-Chang Chen | 2004-08-24 |
| 6764927 | Chemical vapor deposition (CVD) method employing wetting pre-treatment | Ming-Fang Wang, Yeou-Ming Lin, Tuo-Hung Ho, Shih-Chang Chen | 2004-07-20 |
| 6706581 | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices | Tou-Hung Hou, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Shih-Chang Chen | 2004-03-16 |
| 6656764 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Shih-Chang Chen | 2003-12-02 |
| 6455330 | Methods to create high-k dielectric gate electrodes with backside cleaning | Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang | 2002-09-24 |
| 6413885 | Method for patterning semiconductor devices on a silicon substrate using oxynitride film | Pin-Ting Wang | 2002-07-02 |
| 6372642 | Method for patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a silicon substrate using oxynitride film and deep UV lithography | Pin-Ting Wang | 2002-04-16 |
| 6258734 | Method for patterning semiconductor devices on a silicon substrate using oxynitride film | Pin-Ting Wang | 2001-07-10 |
| 6235650 | Method for improved semiconductor device reliability | — | 2001-05-22 |
| 6232234 | Method of reducing in film particle number in semiconductor manufacture | Shih-Chieh Su, Hung-Chuan Chen, Yuh-Min Lin | 2001-05-15 |
| 6221558 | Anti-reflection oxynitride film for polysilicon substrates | John Lin, Hua-Tai Lin, Erik S. Jeng, Hsiao-Chin Tuan | 2001-04-24 |
| 6153541 | Method for fabricating an oxynitride layer having anti-reflective properties and low leakage current | Yue-Feng Cheu, Keng-Chu Lin | 2000-11-28 |
| 6143664 | Method of planarizing a structure having an interpoly layer | Chung-Ju Lee, Yue Chen, Wei-Ray Lin, Yeur-Luen Tu | 2000-11-07 |
| 6133613 | Anti-reflection oxynitride film for tungsten-silicide substrates | John Lin, Hua-Tai Lin | 2000-10-17 |
| 6100137 | Etch stop layer used for the fabrication of an overlying crown shaped storage node structure | Yue Chen, Guei-Chi Guo, Hung-Yi Luo | 2000-08-08 |
| 6048775 | Method to make shallow trench isolation structure by HDP-CVD and chemical mechanical polish processes | Stanley Hsu, Randy (C. H.) Chang, Albert Lin | 2000-04-11 |
| 6037276 | Method for improving patterning of a conductive layer in an integrated circuit | Hua-Tai Lin, Erik S. Jeng | 2000-03-14 |
| 5962344 | Plasma treatment method for PECVD silicon nitride films for improved passivation layers on semiconductor metal interconnections | Yeur-Luen Tu, Shiang-Peng Cheng, Kwong-Jr Tsai | 1999-10-05 |