EJ

Erik S. Jeng

VS Vanguard International Semiconductor: 64 patents #3 of 585Top 1%
AC Applied Intellectual Properties Co.: 8 patents #1 of 3Top 35%
MC Megawin Technology Co.: 2 patents #3 of 20Top 15%
CU Chung Yuan Christian University: 1 patents #145 of 438Top 35%
Overall (All Time): #24,558 of 4,157,543Top 1%
77
Patents All Time

Issued Patents All Time

Showing 1–25 of 77 patents

Patent #TitleCo-InventorsDate
7777267 Manufacture method and structure of a nonvolatile memory Wu Chou, Chih-Hsueh Hung, Chien-Cheng Li 2010-08-17
7473599 Memory capable of storing information and the method of forming and operating the same 2009-01-06
7457154 High density memory array system Tzu-Shih Yen 2008-11-25
7375394 Fringing field induced localized charge trapping memory 2008-05-20
7235848 Nonvolatile memory with spacer trapping structure 2007-06-26
7179708 Process for fabricating non-volatile memory by tilt-angle ion implantation Wu Chou, Li-Kang Wu, Chien-Chen Li 2007-02-20
7072210 Memory array 2006-07-04
7030448 Mask ROM and the method of forming the same and the scheme of reading the device 2006-04-18
6903968 Nonvolatile memory capable of storing multibits binary information and the method of forming the same 2005-06-07
6885072 Nonvolatile memory with undercut trapping structure 2005-04-26
6767792 Fabrication method for forming flash memory device provided with adjustable sharp end structure of the L-shaped floating gate Wen-Ying Wen, Jyh-Long Horng, Bai-Jun Kuo, Chih-Hsueh Hung 2004-07-27
6740927 Nonvolatile memory capable of storing multibits binary information and the method of forming the same 2004-05-25
6649475 Method of forming twin-spacer gate flash device and the structure of the same Wen-Ying Wen, Jyhlong Horng, Bai-Jun Kuo, Chih-Hsueh Hung 2003-11-18
6565759 Etching process Bi-Ling Chen, Hao Liu 2003-05-20
6476488 Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections Bi-Ling Chen, Chien-Sheng Hsieh 2002-11-05
6472717 Method for fabricating reduced contacts using retardation layers H. C. Liu 2002-10-29
6458706 Method of forming contact using non-conformal dielectric liner Eddy Chiang, I-Ping Lee, Kuei-Chuen Ho 2002-10-01
6413813 Method for making DRAM using an oxide plug in the bitline contacts during fabrication 2002-07-02
6376384 Multiple etch contact etching method incorporating post contact etch etching Tzu-Shih Yen, I-Ping Lee, Eddy Chiang 2002-04-23
6306759 Method for forming self-aligned contact with liner Tzu-Shih Yen, Hsiao-Chin Tuan, Chun-Yao Chen, Eddy Chiang, Wen-Shiang Liao 2001-10-23
6278189 High density integrated circuits using tapered and self-aligned contacts Fu-Liang Yang, Tzu-Shih Yen 2001-08-21
6265296 Method for forming self-aligned contacts using a hard mask Tzu-Shih Yen, Hao Liu, Hung-Yi Luo 2001-07-24
6248643 Method of fabricating a self-aligned contact Chien-Sheng Hsieh, Wei-Ray Lin, Fu-Liang Yang, Bor-Ru Sheu 2001-06-19
6245656 Method for producing multi-level contacts Bi-Ling Chen, Shih-Ming Chang 2001-06-12
6239011 Method of self-aligned contact hole etching by fluorine-containing discharges Bi-Ling Chen 2001-05-29