TY

Tzu-Shih Yen

VS Vanguard International Semiconductor: 18 patents #25 of 585Top 5%
AT Advanced Ion Beam Technology: 5 patents #8 of 69Top 15%
AC Applied Intellectual Properties Co.: 1 patents #2 of 3Top 70%
Overall (All Time): #174,500 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #TitleCo-InventorsDate
9209278 Replacement source/drain finFET fabrication Daniel Tang 2015-12-08
9159810 Doping a non-planar semiconductor device Daniel Tang 2015-10-13
9006065 Plasma doping a non-planar semiconductor device Daniel Tang, Tsungnan Cheng 2015-04-14
8871584 Replacement source/drain finFET fabrication Daniel Tang 2014-10-28
8685825 Replacement source/drain finFET fabrication Daniel Tang 2014-04-01
7457154 High density memory array system Erik S. Jeng 2008-11-25
6423646 Method for removing etch-induced polymer film and damaged silicon layer from a silicon surface Hsiu-Lan Lee, Pei-Wen Li 2002-07-23
6376384 Multiple etch contact etching method incorporating post contact etch etching Erik S. Jeng, I-Ping Lee, Eddy Chiang 2002-04-23
6306759 Method for forming self-aligned contact with liner Erik S. Jeng, Hsiao-Chin Tuan, Chun-Yao Chen, Eddy Chiang, Wen-Shiang Liao 2001-10-23
6278189 High density integrated circuits using tapered and self-aligned contacts Erik S. Jeng, Fu-Liang Yang 2001-08-21
6265296 Method for forming self-aligned contacts using a hard mask Erik S. Jeng, Hao Liu, Hung-Yi Luo 2001-07-24
6235621 Method for forming a semiconductor device Erik S. Jeng, Chi-San Wu, Jong-Bor Wang 2001-05-22
6140240 Method for eliminating CMP induced microscratches Fu-Liang Yang, Bih-Tiao Lin, Bi-Ling Chen, Erik S. Jeng 2000-10-31
6136661 Method to fabricate capacitor structures with very narrow features using silyated photoresist Erik S. Jeng 2000-10-24
6124192 Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs Erik S. Jeng, Hung-Yi Luo 2000-09-26
6037216 Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process Hao Liu, Fu-Liang Yang, Wan-Yih Lien 2000-03-14
5994228 Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes Erik S. Jeng, Fu-Liang Yang 1999-11-30
5990018 Oxide etching process using nitrogen plasma Yu-Chun Ho, Hung-Yi Luo 1999-11-23
5962195 Method for controlling linewidth by etching bottom anti-reflective coating Erik S. Jeng 1999-10-05
5904154 Method for removing fluorinated photoresist layers from semiconductor substrates Rong-Wu Chien, Hsiu-Lan Lee 1999-05-18
5899747 Method for forming a tapered spacer Kuo-Chang Wu 1999-05-04
5895740 Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers Rong-Wu Chien 1999-04-20
5780338 Method for manufacturing crown-shaped capacitors for dynamic random access memory integrated circuits Erik S. Jeng 1998-07-14
5688713 Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers Kung Linliu, Erik S. Jeng 1997-11-18