Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6235621 | Method for forming a semiconductor device | Tzu-Shih Yen, Chi-San Wu, Jong-Bor Wang | 2001-05-22 |
| 6221558 | Anti-reflection oxynitride film for polysilicon substrates | Liang-Gi Yao, John Lin, Hua-Tai Lin, Hsiao-Chin Tuan | 2001-04-24 |
| 6211557 | Contact structure using taper contact etching and polycide step | Jun-Cheng Ko | 2001-04-03 |
| 6184081 | Method of fabricating a capacitor under bit line DRAM structure using contact hole liners | Bi-Ling Chen, Wei-Ray Lin, Yu-Chun Ho, Ming-Hong Kuo | 2001-02-06 |
| 6180489 | Formation of finely controlled shallow trench isolation for ULSI process | Fu-Liang Yang, Bih-Tiao Lin, Wei-Ray Lin | 2001-01-30 |
| 6177695 | DRAM using oxide plug in bitline contacts during fabrication | — | 2001-01-23 |
| 6168987 | Method for fabricating crown-shaped capacitor structures | Ing-Ruey Liaw, Rong-Wu Chien | 2001-01-02 |
| 6159839 | Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections | Bi-Ling Chen, Chien-Sheng Hsieh | 2000-12-12 |
| 6150213 | Method of forming a cob dram by using self-aligned node and bit line contact plug | Hung-Yi Luo, Yue Chen | 2000-11-21 |
| 6140240 | Method for eliminating CMP induced microscratches | Fu-Liang Yang, Bih-Tiao Lin, Tzu-Shih Yen, Bi-Ling Chen | 2000-10-31 |
| 6136661 | Method to fabricate capacitor structures with very narrow features using silyated photoresist | Tzu-Shih Yen | 2000-10-24 |
| 6136643 | Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology | Chun-Yao Chen, Ing-Ruey Liaw, Janmye Sung | 2000-10-24 |
| 6124192 | Method for fabricating ultra-small interconnections using simplified patterns and sidewall contact plugs | Tzu-Shih Yen, Hung-Yi Luo | 2000-09-26 |
| 6103588 | Method of forming a contact hole in a semiconductor device | Bi-Ling Chen, Hao Liu | 2000-08-15 |
| 6080620 | Method for fabricating interconnection and capacitors of a DRAM using a simple geometry active area, self-aligned etching, and polysilicon plugs | — | 2000-06-27 |
| 6080662 | Method for forming multi-level contacts using a H-containing fluorocarbon chemistry | Bi-Ling Chen, Hao Liu | 2000-06-27 |
| 6074952 | Method for forming multi-level contacts | Hao Liu, Bi-Ling Chen, Wan-Yih Lien | 2000-06-13 |
| 6071789 | Method for simultaneously fabricating a DRAM capacitor and metal interconnections | Fu-Liang Yang, Bih-Tiao Lin, I-Ping Lee | 2000-06-06 |
| 6060348 | Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology | Fu-Liang Yang, Wei-Ray Lin, Ming-Hong Kuo | 2000-05-09 |
| 6057246 | Method for etching a metal layer with dimensional control | I-Ping Lee, Chyei-Jer Hsieh | 2000-05-02 |
| 6037211 | Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes | Yue Chen, Bi-Ling Chen | 2000-03-14 |
| 6037276 | Method for improving patterning of a conductive layer in an integrated circuit | Hua-Tai Lin, Liang-Gi Yao | 2000-03-14 |
| 6033962 | Method of fabricating sidewall spacers for a self-aligned contact hole | Hung-Yi Luo, Yue Chen, Ming-Horn Tsai | 2000-03-07 |
| 6001704 | Method of fabricating a shallow trench isolation by using oxide/oxynitride layers | Hsu-Li Cheng, Wei-Ray Lin | 1999-12-14 |
| 5994228 | Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes | Fu-Liang Yang, Tzu-Shih Yen | 1999-11-30 |