Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7589990 | Semiconductor ROM device and manufacturing method thereof | Chih-Ta Star Sung, Thomas Chang | 2009-09-15 |
| 7129134 | Fabrication method for flash memory source line and flash memory | Jui-Hsiang Yang, Yue Chen | 2006-10-31 |
| 6762096 | Method for forming a polysilicon spacer with a vertical profile | Fsien-Fu Meng, Chyei-Jer Hsieh, Yu-Chen Ho, Hsu-Li Cheng | 2004-07-13 |
| 6555433 | Method of manufacture of a crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor | — | 2003-04-29 |
| 6476437 | Crown or stack capacitor with a monolithic fin structure | — | 2002-11-05 |
| 6351037 | Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits | Meng-Jaw Cherng | 2002-02-26 |
| 6344392 | Methods of manufacture of crown or stack capacitor with a monolithic fin structure made with a different oxide etching rate in hydrogen fluoride vapor | — | 2002-02-05 |
| 6277719 | Method for fabricating a low resistance Poly-Si/metal gate | Jin-Dong Chern, Kwong-Jr Tsai, Randy C. H. Chang | 2001-08-21 |
| 6249018 | Fabrication method to approach the conducting structure of a DRAM cell with straightforward bit line | Wen-Jya Liang | 2001-06-19 |
| 6239014 | Tungsten bit line structure featuring a sandwich capping layer | — | 2001-05-29 |
| 6171929 | Shallow trench isolator via non-critical chemical mechanical polishing | Fu-Liang Yang, Chung-Ju Lee, Meow-Ru Hsu, Ming-Hong Kuo | 2001-01-09 |
| 6168987 | Method for fabricating crown-shaped capacitor structures | Erik S. Jeng, Rong-Wu Chien | 2001-01-02 |
| 6150247 | Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits | Meng-Jaw Cherng | 2000-11-21 |
| 6136643 | Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology | Erik S. Jeng, Chun-Yao Chen, Janmye Sung | 2000-10-24 |
| 6133599 | Design and a novel process for formation of DRAM bit line and capacitor node contacts | Jan-Mye Sung, Ming-Hong Kuo | 2000-10-17 |
| 6087253 | Method of forming landing plugs for PMOS and NMOS | — | 2000-07-11 |
| 6017614 | Plasma-enhanced chemical vapor deposited SIO.sub.2 /SI.sub.3 N.sub.4 multilayer passivation layer for semiconductor applications | Kwong-Jr Tsai, Shiang-Peng Cheng, Yeur-Luen Tu | 2000-01-25 |
| 6008085 | Design and a novel process for formation of DRAM bit line and capacitor node contacts | Janmye Sung, Ming-Hong Kuo | 1999-12-28 |
| 6008075 | Method for simultaneous formation of contacts between metal layers and fuse windows in semiconductor manufacturing | Wah-Yih Lien | 1999-12-28 |
| 5998279 | Manufacture of a shallow trench isolation device by exposing negative photoresist to increased exposure energy and chemical mechanical planarization | — | 1999-12-07 |
| 5956587 | Method for crown type capacitor in dynamic random access memory | Li-Yeat Chen | 1999-09-21 |
| 5923973 | Method of making greek letter psi shaped capacitor for DRAM circuits | Li-Yeat Chen | 1999-07-13 |
| 5905293 | LDD spacers in MOS devices with double spacers | Erik S. Jeng | 1999-05-18 |
| 5874359 | Small contacts for ultra large scale integration semiconductor devices without separation ground rule | Jau-Hwang Ho, Meng-Jaw Cherng | 1999-02-23 |
| 5851603 | Method for making a plasma-enhanced chemical vapor deposited SiO.sub.2 Si.sub.3 N.sub.4 multilayer passivation layer for semiconductor applications | Kwong-Jr Tsai, Shiang-Peng Cheng, Yeur-Luen Tu | 1998-12-22 |