Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12125910 | Transistor structure with increased gate dielectric thickness between gate-to-drain overlap region | Chao-Chun Lu, Chun-Nan LU | 2024-10-22 |
| 10479676 | Apparatus and methods for integrated MEMS devices | Ben Lee, Wen-Chih Chen, Wensen Tsai | 2019-11-19 |
| 10046966 | Apparatus and methods for integrated MEMS devices | Ben Lee, Wen-Chih Chen, Wensen Tsai | 2018-08-14 |
| 9935109 | Dynamic memory structure | Nicky C. Lu | 2018-04-03 |
| 9685449 | Dynamic memory structure | Nicky C. Lu | 2017-06-20 |
| 9397103 | Dynamic memory structure | Nicky C. Lu | 2016-07-19 |
| 9105506 | Dynamic memory structure | Nicky C. Lu | 2015-08-11 |
| 8724362 | Transistor circuit layout structure | — | 2014-05-13 |
| 8659068 | Dynamic memory structure | — | 2014-02-25 |
| 8331178 | Memory device capable of operation in a burn in stress mode, method for performing burn in stress on a memory device, and method for detecting leakage current of a memory device | Shi-Huei Liu, Tzu-Hao Chen, Te-Yi Yu | 2012-12-11 |
| 6261923 | Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP | Wei-Ray Lin, Fu-Liang Yang | 2001-07-17 |
| 6184081 | Method of fabricating a capacitor under bit line DRAM structure using contact hole liners | Erik S. Jeng, Bi-Ling Chen, Wei-Ray Lin, Yu-Chun Ho | 2001-02-06 |
| 6171929 | Shallow trench isolator via non-critical chemical mechanical polishing | Fu-Liang Yang, Chung-Ju Lee, Meow-Ru Hsu, Ing-Ruey Liaw | 2001-01-09 |
| 6133599 | Design and a novel process for formation of DRAM bit line and capacitor node contacts | Jan-Mye Sung, Ing-Ruey Liaw | 2000-10-17 |
| 6060348 | Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology | Fu-Liang Yang, Wei-Ray Lin, Erik S. Jeng | 2000-05-09 |
| 6057210 | Method of making a shallow trench isolation for ULSI formation via in-direct CMP process | Fu-Liang Yang, Wei-Ray Lin | 2000-05-02 |
| 6017813 | Method for fabricating a damascene landing pad | — | 2000-01-25 |
| 6008085 | Design and a novel process for formation of DRAM bit line and capacitor node contacts | Janmye Sung, Ing-Ruey Liaw | 1999-12-28 |
| 5658822 | Locos method with double polysilicon/silicon nitride spacer | Shye-Lin Wu, Hsi-Chuan Chen | 1997-08-19 |
| 5643824 | Method of forming nitride sidewalls having spacer feet in a locos process | Rong-Wu Chien, Hsu-Li Cheng | 1997-07-01 |
| 5092266 | Solder leveler | — | 1992-03-03 |
| 4775090 | Pin head assembly | — | 1988-10-04 |