Issued Patents All Time
Showing 25 most recent of 212 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7491633 | High switching speed two mask schottky diode with high field breakdown | — | 2009-02-17 |
| 7368371 | Silicon carbide Schottky diode and method of making the same | — | 2008-05-06 |
| 7187046 | Method of forming an N channel and P channel finfet device on the same semiconductor substrate | Chung-Cheng Wu | 2007-03-06 |
| 7078780 | Schottky barrier diode and method of making the same | — | 2006-07-18 |
| 7064408 | Schottky barrier diode and method of making the same | — | 2006-06-20 |
| 6998694 | High switching speed two mask Schottky diode with high field breakdown | — | 2006-02-14 |
| 6936905 | Two mask shottky diode with locos structure | — | 2005-08-30 |
| 6825073 | Schottky diode with high field breakdown and low reverse leakage current | — | 2004-11-30 |
| 6770516 | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate | Chung-Cheng Wu | 2004-08-03 |
| 6649308 | Ultra-short channel NMOSFETS with self-aligned silicide contact | — | 2003-11-18 |
| 6569729 | Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application | Chung-Cheng Wu | 2003-05-27 |
| 6555438 | Method for fabricating MOSFETs with a recessed self-aligned silicide contact and extended source/drain junctions | — | 2003-04-29 |
| 6548362 | Method of forming MOSFET with buried contact and air-gap gate structure | — | 2003-04-15 |
| 6432785 | Method for fabricating ultra short channel PMOSFET with buried source/drain junctions and self-aligned silicide | — | 2002-08-13 |
| 6358818 | Method for forming trench isolation regions | — | 2002-03-19 |
| 6355540 | Stress-free shallow trench isolation | — | 2002-03-12 |
| 6348390 | Method for fabricating MOSFETS with a recessed self-aligned silicide contact and extended source/drain junctions | — | 2002-02-19 |
| 6342422 | Method for forming MOSFET with an elevated source/drain | — | 2002-01-29 |
| 6331456 | Fipos method of forming SOI CMOS structure | — | 2001-12-18 |
| 6329264 | Method for forming a ragged polysilcon crown-shaped capacitor for a memory cell | — | 2001-12-11 |
| 6323094 | Method to fabricate deep sub-.mu.m CMOSFETs | — | 2001-11-27 |
| 6316316 | Method of forming high density and low power flash memories with a high capacitive-coupling ratio | — | 2001-11-13 |
| 6303417 | Method of forming self-aligned planarization twin-well by using fewer mask counts for CMOS transistors | — | 2001-10-16 |
| 6294416 | Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts | — | 2001-09-25 |
| 6294797 | MOSFET with an elevated source/drain | — | 2001-09-25 |