Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6198121 | Method fabricating a DRAM cell with an area equal to four times the used minimum feature | — | 2001-03-06 |
| 6180453 | Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared | Chih-Yuan Lu | 2001-01-30 |
| 6163047 | Method of fabricating a self aligned contact for a capacitor over bitline, (COB), memory cell | Nicky C. Lu | 2000-12-19 |
| 6136643 | Method for fabricating capacitor-over-bit-line dynamic random access memory (DRAM) using self-aligned contact etching technology | Erik S. Jeng, Chun-Yao Chen, Ing-Ruey Liaw | 2000-10-24 |
| 6137130 | Capacitor over bit line structure using a straight bit line shape | — | 2000-10-24 |
| 6025227 | Capacitor over bit line structure using a straight bit line shape | — | 2000-02-15 |
| 6008085 | Design and a novel process for formation of DRAM bit line and capacitor node contacts | Ing-Ruey Liaw, Ming-Hong Kuo | 1999-12-28 |
| 6008084 | Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance | — | 1999-12-28 |
| 5943581 | Method of fabricating a buried reservoir capacitor structure for high-density dynamic random access memory (DRAM) circuits | Chih-Yuan Lu | 1999-08-24 |
| 5879997 | Method for forming self aligned polysilicon contact | Kuo-Hua Lee | 1999-03-09 |
| 5879986 | Method for fabrication of a one gigabit capacitor over bit line DRAM cell with an area equal to eight times the used minimum feature | — | 1999-03-09 |
| 5858831 | Process for fabricating a high performance logic and embedded dram devices on a single semiconductor chip | — | 1999-01-12 |
| 5821142 | Method for forming a capacitor with a multiple pillar structure | Howard C. Kirsch, Chih-Yuan Lu | 1998-10-13 |
| 5808335 | Reduced mask DRAM process | — | 1998-09-15 |
| 5792680 | Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor | Chih-Yuan Lu, Howard C. Kirsch | 1998-08-11 |
| 5789291 | Dram cell capacitor fabrication method | — | 1998-08-04 |
| 5753551 | Memory cell array with a self-aligned, buried bit line | — | 1998-05-19 |
| 5729056 | Low cycle time CMOS process | — | 1998-03-17 |
| 5679589 | FET with gate spacer | Kuo-Hua Lee, Chih-Yuan Lu | 1997-10-21 |
| 5656510 | Method for manufacturing gate oxide capacitors including wafer backside dielectric and implantation electron flood gun current control | Terry Chrapacz, Kenneth Gordon Moerschel, William A. Possanza, Michael Allen Prozonic | 1997-08-12 |
| 5573962 | Low cycle time CMOS process | — | 1996-11-12 |
| 5559360 | Inductor for high frequency circuits | Tzu-Yin Chiu, Frank M. Erceg, Duk-Young Jeon | 1996-09-24 |
| 5550078 | Reduced mask DRAM process | — | 1996-08-27 |
| 5547893 | method for fabricating an embedded vertical bipolar transistor and a memory cell | — | 1996-08-20 |
| 5488248 | Memory integrated circuit | Kuo-Hua Lee | 1996-01-30 |