Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8012824 | Process to make high-K transistor dielectrics | Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang | 2011-09-06 |
| 8003548 | Atomic layer deposition | Chen-Hua Yu | 2011-08-23 |
| 7998820 | High-k gate dielectric and method of manufacture | Chen-Hua Yu | 2011-08-16 |
| 7910467 | Method for treating layers of a gate stack | Yu-Rung Hsu, Chen-Hua Yu | 2011-03-22 |
| 7892909 | Polysilicon gate formation by in-situ doping | Chen-Hua Yu, Ding-Yuan Chen, Chu-Yun Fu, Chen-Nan Yeh | 2011-02-22 |
| 7892961 | Methods for forming MOS devices with metal-inserted polysilicon gate stack | Chen-Hua Yu, Cheng-Tung Lin | 2011-02-22 |
| 7851377 | Chemical vapor deposition process | Chen-Hua Yu | 2010-12-14 |
| 7732878 | MOS devices with continuous contact etch stop layer | Shiang-Bau Wang, Huan-Just Lin, Peng-Fu Hsu, Jin Ying, Hun-Jan Tao | 2010-06-08 |
| 7592619 | Epitaxy layer and method of forming the same | Pang-Yen Tsai, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen | 2009-09-22 |
| 7410854 | Method of making FUSI gate and resulting structure | Hun-Jan Tao, Shih-Chang Chen, Mong-Song Liang | 2008-08-12 |
| 7393766 | Process for integration of a high dielectric constant gate insulator layer in a CMOS device | Ming-Fang Wang, Chien-Hao Chen, Shih-Chang Chen | 2008-07-01 |
| 7357838 | Relaxed silicon germanium substrate with low defect density | Chun-Chieh Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang +4 more | 2008-04-15 |
| 7351994 | Noble high-k device | Tien-Chih Chang, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang | 2008-04-01 |
| 7303996 | High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics | Ming-Fang Wang, Tuo-Hung Hou, Kai-Lin Mai, Shih-Chang Chen | 2007-12-04 |
| 7271450 | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures | Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Chih-Chang Chen | 2007-09-18 |
| 7229919 | Semiconductor device having a random grained polysilicon layer and a method for its manufacture | Chia-Lin Chen, Shih-Chang Chen | 2007-06-12 |
| 7202142 | Method for producing low defect density strained -Si channel MOSFETS | Kuen-Chyr Lee, Shih-Chang Chen, Mong-Song Liang | 2007-04-10 |
| 7175709 | Epitaxy layer and method of forming the same | Pang-Yen Tsai, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen | 2007-02-13 |
| 7105393 | Strained silicon layer fabrication with reduced dislocation defect density | Tien-Chih Chang, CC Lin, Shin-Chang Chen, Mong-Song Liang | 2006-09-12 |
| 7087480 | Process to make high-k transistor dielectrics | Ming-Fang Wang, Shih-Chang Chen, Mon-Song Liang | 2006-08-08 |
| 7071066 | Method and structure for forming high-k gates | Ming-Fang Wang, Chia-Lin Chen, Chih-Wei Yang, Chi-Chun Chen, Tuo-Hung Hou +2 more | 2006-07-04 |
| 7057299 | Alignment mark configuration | Jaw-Jung Shin | 2006-06-06 |
| 7030024 | Dual-gate structure and method of fabricating integrated circuits having dual-gate structures | Tuo-Hung Ho, Ming-Fang Wang, Chi-Chun Chen, Chih-Wei Yang, Chih-Chang Chen | 2006-04-18 |
| 7018879 | Method of making an ultrathin silicon dioxide gate with improved dielectric properties using NH3 nitridation and post-deposition rapid thermal annealing | Ming-Fang Wang, Chien-Hao Chen, Shih-Chang Chen | 2006-03-28 |
| 7012009 | Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process | Kuen-Chyr Lee, Tien-Chih Chang, Chia-Lin Chen, Shih-Chang Chen, Mong-Song Liang | 2006-03-14 |