Issued Patents All Time
Showing 1,676–1,700 of 1,955 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8058150 | Particle free wafer separation | Weng-Jin Wu, Ku-Feng Yang, Jung-Chih Hu, Wen-Chih Chiou | 2011-11-15 |
| 8058669 | Light-emitting diode integration scheme | Ding-Yuan Chen, Wen-Chih Chiou | 2011-11-15 |
| 8053277 | Three-dimensional integrated circuits with protection layers | Wen-Chih Chiou, Weng-Jin Wu, Hung-Jung Tu, Ku-Feng Yang | 2011-11-08 |
| 8053900 | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect | Wen-Chih Chiou, Weng-Jin Wu | 2011-11-08 |
| 8048717 | Method and system for bonding 3D semiconductor devices | Chung-Shi Liu, Yuh-Jier Mii, Yuan-Chen Sun | 2011-11-01 |
| 8048723 | Germanium FinFETs having dielectric punch-through stoppers | Cheng-Hung Chang, Yu-Rung Hsu, Chen-Yi Lee, Shih-Ting Hung, Chen-Nan Yeh | 2011-11-01 |
| 8044409 | III-nitride based semiconductor structure with multiple conductive tunneling layer | Chia-Lin Yu, Ding-Yuan Chen, Wen-Chih Chiou | 2011-10-25 |
| 8034711 | Bonding structure and fabrication thereof | Horng-Huei Tseng | 2011-10-11 |
| 8030781 | Bond pad structure having dummy plugs and/or patterns formed therearound | Tien-I Bao | 2011-10-04 |
| 8030666 | Group-III nitride epitaxial layer on silicon substrate | Ding-Yuan Chen | 2011-10-04 |
| 8030776 | Integrated circuit with protective structure | Shin-Puu Jeng, Shang-Yun Hou, Hao-Yi Tsai, Hsien-Wei Chen, Hsiu-Ping Wei | 2011-10-04 |
| 8013445 | Low resistance high reliability contact via and metal line structure for semiconductor device | Hsiang-Huan Lee, Ming-Han Lee, Ming-Shih Yeh | 2011-09-06 |
| 8003548 | Atomic layer deposition | Liang-Gi Yao | 2011-08-23 |
| 7998820 | High-k gate dielectric and method of manufacture | Liang-Gi Yao | 2011-08-16 |
| 7993998 | CMOS devices having dual high-mobility channels | Ding-Yuan Chen | 2011-08-09 |
| 7989318 | Method for stacking semiconductor dies | Ku-Feng Yang, Weng-Jin Wu, Wen-Chih Chiou | 2011-08-02 |
| 7977772 | Hybrid metal fully silicided (FUSI) gate | Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh | 2011-07-12 |
| 7968451 | Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections | Chung-Chi Ko, Chia-Cheng Chou, Keng-Chu Lin, Tien-I Bao | 2011-06-28 |
| 7964496 | Schemes for forming barrier layers for copper in interconnect structures | Hai-Ching Chen, Tien-I Bao | 2011-06-21 |
| 7960290 | Method of fabricating a semiconductor device | Wen-Chih Chiou, Weng-Jin Wu | 2011-06-14 |
| 7956448 | Stacked structures and methods of fabricating stacked structures | Wen-Chih Chiou, Weng-Jin Wu, Jean Wang | 2011-06-07 |
| 7947588 | Structure and method for a CMOS device with doped conducting metal oxide as the gate electrode | Cheng-Tung Lin, Hsiang-Yi Wang, Yung-Sheng Chiu, Chia-Lin Yu | 2011-05-24 |
| 7939889 | Reducing resistance in source and drain regions of FinFETs | Yu-Rung Hsu, Chen-Nan Yeh, Cheng-Hung Chang | 2011-05-10 |
| 7939941 | Formation of through via before contact processing | Wen-Chih Chiou, Weng-Jin Wu | 2011-05-10 |
| 7918251 | Substrate carrier and facility interface and apparatus including same | Yi-Li Hsiao | 2011-04-05 |