WF

Warren M. Farnworth

Micron: 760 patents #3 of 6,345Top 1%
AI Aptina Imaging: 7 patents #36 of 332Top 15%
RR Round Rock Research: 3 patents #66 of 239Top 30%
📍 Nampa, ID: #1 of 306 inventorsTop 1%
🗺 Idaho: #2 of 8,810 inventorsTop 1%
Overall (All Time): #113 of 4,157,543Top 1%
778
Patents All Time

Issued Patents All Time

Showing 201–225 of 778 patents

Patent #TitleCo-InventorsDate
7065868 Methods for installing a circuit device Larry D. Kinsman, Mike Brooks, Walter L. Moden, Terry R. Lee 2006-06-27
7064010 Methods of coating and singulating wafers Kyle K. Kirby, William M. Hiatt 2006-06-20
7063524 Apparatus for increased dimensional accuracy of 3-D object creation Kevin G. Duesman 2006-06-20
7060526 Wafer level methods for fabricating multi-dice chip scale semiconductor components Alan G. Wood, William M. Hiatt, James M. Wark, David R. Hembree, Kyle K. Kirby +1 more 2006-06-13
7049840 Hybrid interconnect and system for testing semiconductor dice David R. Hembree, Salman Akram, Alan G. Wood, James M. Wark, Derek Gochnour 2006-05-23
7043831 Method for fabricating a test interconnect for bumped semiconductor components by forming recesses and cantilevered leads on a substrate Salman Akram 2006-05-16
7043830 Method of forming conductive bumps 2006-05-16
7042080 Semiconductor interconnect having compliant conductive contacts Kyle K. Kirby 2006-05-09
7040930 Modular sockets using flexible interconnects David J. Corisis, Salman Akram 2006-05-09
7034561 Device and method for isolating a short-circuited integrated circuit (IC) from other ICs on a semiconductor wafer William K. Waller, Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud 2006-04-25
7034560 Device and method for testing integrated circuit dice in an integrated circuit module James M. Wark, Eric S. Nelson, Kevin G. Duesman 2006-04-25
7030010 Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures Dale W. Collins, Steven M. McDonald 2006-04-18
7029949 Method for fabricating encapsulated semiconductor components having conductive vias Alan G. Wood, Trung T. Doan 2006-04-18
7026835 Engagement probe having a grouping of projecting apexes for engaging a conductive pad Malcolm Grief, Gurtej S. Sandhu 2006-04-11
7022533 Substrate mapping Derek Gochnour 2006-04-04
7021915 Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length 2006-04-04
7003874 Methods of bonding solder balls to bond pads on a substrate Alan G. Wood 2006-02-28
7002362 Test system for bumped semiconductor components Salman Akram 2006-02-21
6998717 Multi-dice chip scale semiconductor components Alan G. Wood, William M. Hiatt, James M. Wark, David R. Hembree, Kyle K. Kirby +1 more 2006-02-14
6998344 Method for fabricating semiconductor components by forming conductive members using solder Salman Akram, Alan G. Wood 2006-02-14
6998334 Semiconductor devices with permanent polymer stencil and method for manufacturing the same Alan G. Wood, James M. Wark, David R. Hembree, Syed Sajid Ahmad, Michael E. Hess +1 more 2006-02-14
6995577 Contact for semiconductor components Salman Akram 2006-02-07
6992398 Underfill and encapsulation of carrier substrate-mounted flip-chip components 2006-01-31
6984583 Stereolithographic method for forming insulative coatings for via holes in semiconductor devices 2006-01-10
6983536 Method and apparatus for manufacturing known good semiconductor die Alan G. Wood 2006-01-10