Issued Patents All Time
Showing 251–275 of 778 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6909929 | Stereolithographic method and apparatus for packaging electronic components | Mark S. Johnson | 2005-06-21 |
| 6906418 | Semiconductor component having encapsulated, bonded, interconnect contacts | William M. Hiatt, Charles M. Watkins, Nishant Sinha | 2005-06-14 |
| 6903465 | Method and apparatus for a semiconductor package for vertical surface mounting | Larry D. Kinsman, Walter L. Moden | 2005-06-07 |
| 6903443 | Semiconductor component and interconnect having conductive members and contacts on opposing sides | Alan G. Wood, David R. Hembree | 2005-06-07 |
| 6900459 | Apparatus for automatically positioning electronic dice within component packages | Alan G. Wood, John O. Jacobson, David R. Hembree, James M. Wark, Jennifer L. Folaron +3 more | 2005-05-31 |
| 6897089 | Method and system for fabricating semiconductor components using wafer level contact printing | — | 2005-05-24 |
| 6896837 | Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length | — | 2005-05-24 |
| 6893804 | Surface smoothing of stereolithographically formed 3-D objects | Kevin G. Duesman | 2005-05-17 |
| 6892453 | Method for forming an encapsulation device | — | 2005-05-17 |
| 6890844 | Methods and apparatus for forming solder balls | — | 2005-05-10 |
| 6890801 | Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages | — | 2005-05-10 |
| 6888159 | Substrate mapping | Derek Gochnour | 2005-05-03 |
| 6887787 | Method for fabricating semiconductor components with conductors having wire bondable metalization layers | — | 2005-05-03 |
| 6884642 | Wafer-level testing apparatus and method | Steven M. McDonald | 2005-04-26 |
| 6881607 | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography | — | 2005-04-19 |
| 6876089 | Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer | Salman Akram, Alan G. Wood | 2005-04-05 |
| 6875640 | Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed | Alan G. Wood | 2005-04-05 |
| 6875632 | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography | — | 2005-04-05 |
| 6858891 | Nanotube semiconductor devices and methods for making the same | Kevin G. Duesman | 2005-02-22 |
| 6857183 | Methods of bonding solder balls to bond pads on a substrate, and bonding frames | Alan G. Wood | 2005-02-22 |
| 6853210 | Test interconnect having suspended contacts for bumped semiconductor components | Salman Akram | 2005-02-08 |
| 6852999 | Reduced terminal testing system | Leland R. Nevill, Raymond J. Beffa, Eugene H. Cloud | 2005-02-08 |
| 6852627 | Conductive through wafer vias | Nishant Sinha | 2005-02-08 |
| 6851597 | Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems | David R. Hembree, Michael E. Hess, John O. Jacobson, Alan G. Wood | 2005-02-08 |
| 6841883 | Multi-dice chip scale semiconductor components and wafer level methods of fabrication | Alan G. Wood, William M. Hiatt, James M. Wark, David R. Hembree, Kyle K. Kirby +1 more | 2005-01-11 |