Issued Patents All Time
Showing 25 most recent of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848323 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2023-12-19 |
| 11508657 | Semiconductor devices having 3-dimensional inductive structures | James E. Davis | 2022-11-22 |
| 11056467 | Semiconductor devices with through silicon vias and package-level configurability | James E. Davis, Warren L. Boyer | 2021-07-06 |
| 10930645 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2021-02-23 |
| 10867991 | Semiconductor devices with package-level configurability | James E. Davis, Warren L. Boyer, Jeffrey P. Wright | 2020-12-15 |
| 10811372 | Semiconductor devices with post-probe configurability | James E. Davis, Jeffrey P. Wright, Warren L. Boyer | 2020-10-20 |
| 10784192 | Semiconductor devices having 3-dimensional inductive structures | James E. Davis | 2020-09-22 |
| 10580767 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2020-03-03 |
| 10483241 | Semiconductor devices with through silicon vias and package-level configurability | James E. Davis, Warren L. Boyer | 2019-11-19 |
| 10453829 | Method and apparatus for reducing capacitance of input/output pins of memory device | Merri L. Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, James Mathew +1 more | 2019-10-22 |
| 10403585 | Semiconductor devices with post-probe configurability | James E. Davis, Jeffrey P. Wright, Warren L. Boyer | 2019-09-03 |
| 10312232 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2019-06-04 |
| 10283462 | Semiconductor devices with post-probe configurability | James E. Davis, Jeffrey P. Wright, Warren L. Boyer | 2019-05-07 |
| 10128229 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2018-11-13 |
| 8541836 | Recessed access device for a memory | Kurt D. Beigel, Jigish Trivedi | 2013-09-24 |
| 8431980 | Random access memory device utilizing a vertically oriented select transistor | Thomas W. Voshell, Lucien J. Bissey | 2013-04-30 |
| 8319280 | Recessed access device for a memory | Kurt D. Beigel, Jigish Trivedi | 2012-11-27 |
| 8035160 | Recessed access device for a memory | Kurt D. Beigel, Jigish Trivedi | 2011-10-11 |
| 7777264 | Random access memory device utilizing a vertically oriented select transistor | Thomas W. Voshell, Lucien J. Bissey | 2010-08-17 |
| 7730372 | Device and method for testing integrated circuit dice in an integrated circuit module | Warren M. Farnworth, James M. Wark, Eric S. Nelson | 2010-06-01 |
| 7645671 | Recessed access device for a memory | Kurt D. Beigel, Jigish Trivedi | 2010-01-12 |
| 7646016 | Method for automated testing of the modulation transfer function in image sensors | Jeffrey D. Bruce, Peter P. Altice, Jr., Moshe Reuven, Donald E. Robinson, Ed Jenkins +1 more | 2010-01-12 |
| 7519881 | Device and method for testing integrated circuit dice in an integrated circuit module | Warren M. Farnworth, James M. Wark, Eric S. Nelson | 2009-04-14 |
| 7375793 | Apparatus for photolithographic processing | Randal W. Chance | 2008-05-20 |
| 7336522 | Apparatus and method to reduce undesirable effects caused by a fault in a memory device | Scott J. Derner, Stephen R. Porter, Scot M. Graham, Ethan Williford | 2008-02-26 |