Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12362244 | Memory device including circuitry under bond pads | Chiara Cerafogli, Kenneth W. Marr, Brian J. Soderling, Michael P. Violette, Joshua Daniel Tomayer | 2025-07-15 |
| 12354669 | Discharge circuits | Kenneth W. Marr, Chiara Cerafogli | 2025-07-08 |
| 11908812 | Multi-die memory device with peak current reduction | Yui Shimizu | 2024-02-20 |
| 11901727 | Apparatuses and method for over-voltage event protection | Michael Chaine | 2024-02-13 |
| 11848323 | Semiconductor devices with package-level configurability | John B. Pusey, Zhiping Yin, Kevin G. Duesman | 2023-12-19 |
| 11798935 | Apparatus with voltage protection mechanism | Milind Nemchand Furia, Michael Chaine, Eric J. Smith | 2023-10-24 |
| 11508657 | Semiconductor devices having 3-dimensional inductive structures | Kevin G. Duesman | 2022-11-22 |
| 11424169 | Memory device including circuitry under bond pads | Chiara Cerafogli, Kenneth W. Marr, Brian J. Soderling, Michael P. Violette, Joshua Daniel Tomayer | 2022-08-23 |
| 11398468 | Apparatus with voltage protection mechanism | Milind Nemchand Furia, Michael Chaine, Eric J. Smith | 2022-07-26 |
| 11183837 | Apparatuses and method for over-voltage event protection | Michael Chaine | 2021-11-23 |
| 11056467 | Semiconductor devices with through silicon vias and package-level configurability | Kevin G. Duesman, Warren L. Boyer | 2021-07-06 |
| 10930645 | Semiconductor devices with package-level configurability | John B. Pusey, Zhiping Yin, Kevin G. Duesman | 2021-02-23 |
| 10867991 | Semiconductor devices with package-level configurability | Kevin G. Duesman, Warren L. Boyer, Jeffrey P. Wright | 2020-12-15 |
| 10811372 | Semiconductor devices with post-probe configurability | Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer | 2020-10-20 |
| 10784192 | Semiconductor devices having 3-dimensional inductive structures | Kevin G. Duesman | 2020-09-22 |
| 10580767 | Semiconductor devices with package-level configurability | John B. Pusey, Zhiping Yin, Kevin G. Duesman | 2020-03-03 |
| 10483241 | Semiconductor devices with through silicon vias and package-level configurability | Kevin G. Duesman, Warren L. Boyer | 2019-11-19 |
| 10453829 | Method and apparatus for reducing capacitance of input/output pins of memory device | Merri L. Carlson, Hongbin Zhu, Gordon A. Haller, Kevin G. Duesman, James Mathew +1 more | 2019-10-22 |
| 10403585 | Semiconductor devices with post-probe configurability | Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer | 2019-09-03 |
| 10312232 | Semiconductor devices with package-level configurability | John B. Pusey, Zhiping Yin, Kevin G. Duesman | 2019-06-04 |
| 10283462 | Semiconductor devices with post-probe configurability | Kevin G. Duesman, Jeffrey P. Wright, Warren L. Boyer | 2019-05-07 |
| 10193334 | Apparatuses and method for over-voltage event protection | Michael Chaine | 2019-01-29 |
| 10128229 | Semiconductor devices with package-level configurability | John B. Pusey, Zhiping Yin, Kevin G. Duesman | 2018-11-13 |
| 9391062 | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes | Michael Chaine | 2016-07-12 |
| 9281682 | Apparatuses and method for over-voltage event protection | Michael Chaine | 2016-03-08 |