Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11901727 | Apparatuses and method for over-voltage event protection | James E. Davis | 2024-02-13 |
| 11798935 | Apparatus with voltage protection mechanism | James E. Davis, Milind Nemchand Furia, Eric J. Smith | 2023-10-24 |
| 11398468 | Apparatus with voltage protection mechanism | James E. Davis, Milind Nemchand Furia, Eric J. Smith | 2022-07-26 |
| 11183837 | Apparatuses and method for over-voltage event protection | James E. Davis | 2021-11-23 |
| 10193334 | Apparatuses and method for over-voltage event protection | James E. Davis | 2019-01-29 |
| 9705318 | Over-limit electrical condition protection circuits for integrated circuits | Xiaofeng Fan | 2017-07-11 |
| 9607930 | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods | Jeffery W. Janzen, Kyle K. Kirby, William M. Hiatt | 2017-03-28 |
| 9490631 | Over-limit electrical condition protection circuits and methods | Xiaofeng Fan, John D. Porter | 2016-11-08 |
| 9391062 | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes | James E. Davis | 2016-07-12 |
| 9343368 | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods | Jeffery W. Janzen, Kyle K. Kirby, William M. Hiatt | 2016-05-17 |
| 9281682 | Apparatuses and method for over-voltage event protection | James E. Davis | 2016-03-08 |
| 9209620 | Combination ESD protection circuits and methods | Xiaofeng Fan | 2015-12-08 |
| 8772086 | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods | Jeffery W. Janzen, Kyle K. Kirby, William M. Hiatt | 2014-07-08 |
| 8724268 | Over-limit electrical condition protection circuits and methods | Xiaofeng Fan, John D. Porter | 2014-05-13 |
| 8693148 | Over-limit electrical condition protection circuits for integrated circuits | Xiaofeng Fan | 2014-04-08 |
| 8611058 | Combination ESD protection circuits and methods | Xaiofeng Fan | 2013-12-17 |
| 8404521 | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods | Jeffery W. Janzen, Kyle K. Kirby, William M. Hiatt | 2013-03-26 |
| 8253230 | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods | Jeffery W. Janzen, Kyle K. Kirby, William M. Hiatt | 2012-08-28 |
| 7903379 | Cascode I/O driver with improved ESD operation | Manny K. F. Ma | 2011-03-08 |
| 7253064 | Cascode I/O driver with improved ESD operation | Manny K. F. Ma | 2007-08-07 |
| 7160795 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Brent Keeth, Salman Akram, Troy A. Manning, Brian Johnson +3 more | 2007-01-09 |
| 6909196 | Method and structures for reduced parasitic capacitance in integrated circuit metallizations | Shubneesh Batra, Brent Keeth, Salman Akram, Troy A. Manning, Brian Johnson +3 more | 2005-06-21 |
| 6809386 | Cascode I/O driver with improved ESD operation | Manny K. F. Ma | 2004-10-26 |
| 6624660 | CMOS output driver for semiconductor device and related method for improving latch-up immunity in a CMOS output driver | Wen Li, Manny K. F. Ma | 2003-09-23 |
| 6534833 | Semiconductor device with protection circuitry and method | Charvaka Duvvury, Puvvada Venugopal | 2003-03-18 |