JC

Jose Alvin Caparas

SC Stats Chippac: 43 patents #25 of 425Top 6%
SS St Assembly Test Services: 5 patents #13 of 63Top 25%
JC Jcet Semiconductor (Shaoxing) Co.: 2 patents #6 of 38Top 20%
📍 Singapore, SG: #69 of 13,971 inventorsTop 1%
Overall (All Time): #54,547 of 4,157,543Top 2%
50
Patents All Time

Issued Patents All Time

Showing 1–25 of 50 patents

Patent #TitleCo-InventorsDate
11127668 Semiconductor device and method of forming double-sided fan-out wafer level package Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh 2021-09-21
10622293 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP) Seung Wook Yoon, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao +1 more 2020-04-14
10453785 Semiconductor device and method of forming double-sided fan-out wafer level package Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh 2019-10-22
10446523 Semiconductor device and method of forming wire studs as vertical interconnect in FO-WLP Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Yang Tan 2019-10-15
10297556 Semiconductor device and method of controlling warpage in reconstituted wafer Kian Meng Heng, Hin Hwa Goh, Kang Chen, Seng Guan Chow, Yaojian Lin 2019-05-21
10163747 Semiconductor device and method of controlling warpage in reconstituted wafer Kian Meng Heng, Hin Hwa Goh, Kang Chen, Seng Guan Chow, Yaojian Lin 2018-12-25
9607965 Semiconductor device and method of controlling warpage in reconstituted wafer Kian Meng Heng, Hin Hwa Goh, Kang Chen, Seng Guan Chow, Yaojian Lin 2017-03-28
9443797 Semiconductor device having wire studs as vertical interconnect in FO-WLP Pandi C. Marimuthu, Sheila Marie L. Alvarez, Yaojian Lin, Yang Tan 2016-09-13
9293401 Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP) Seung Wook Yoon, Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Xusheng Bao +1 more 2016-03-22
9281259 Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in FO-WLCSP Yaojian Lin, Kang Chen, Glenn Omandam 2016-03-08
9153544 Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die Reza A. Pagaila, Pandi C. Marimuthu 2015-10-06
9142428 Semiconductor device and method of forming FO-WLCSP with multiple encapsulants Yaojian Lin, Kang Chen, Hin Hwa Goh 2015-09-22
9076737 Integrated circuit packaging system with bumps and method of manufacture thereof Zigmund Ramirez Camacho, Emmanuel Espiritu, Lionel Chien Hui Tay 2015-07-07
9059157 Integrated circuit packaging system with substrate and method of manufacture thereof Yaojian Lin, Il Kwon Shim, JunMo Koo 2015-06-16
9054083 Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh +1 more 2015-06-09
8710635 Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die Reza A. Pagaila, Pandi C. Marimuthu 2014-04-29
8698294 Integrated circuit package system including wide flange leadframe Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Jeffrey D. Punzalan 2014-04-15
8664038 Integrated circuit packaging system with stacked paddle and method of manufacture thereof Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay 2014-03-04
8659162 Semiconductor device having an interconnect structure with TSV using encapsulant for structural support Nathapong Suthiwongsunthorn, Pandi C. Marimuthu, Jae Hun Ku, Glenn Omandam, Hin Hwa Goh +1 more 2014-02-25
8648470 Semiconductor device and method of forming FO-WLCSP with multiple encapsulants Yaojian Lin, Kang Chen, Hin Hwa Goh 2014-02-11
8610286 Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP Yaojian Lin, Kang Chen, Glenn Omandam 2013-12-17
8569872 Integrated circuit package system with lead-frame paddle scheme for single axis partial saw isolation Henry Descalzo Bathan, Il Kwon Shim, Zigmund Ramirez Camacho, Philip Lyndon Cablao 2013-10-29
8502376 Wirebondless wafer level package with plated bumps and interconnects Zigmund Ramirez Camacho, Dioscoro A. Merilo, Lionel Chien Hui Tay 2013-08-06
8455988 Integrated circuit package system with bumped lead and nonbumped lead Zigmund Ramirez Camacho 2013-06-04
8399306 Integrated circuit packaging system with transparent encapsulation and method of manufacture thereof JunMo Koo, Pandi C. Marimuthu, Jae Hun Ku, Shariff Dzafir 2013-03-19