Issued Patents All Time
Showing 25 most recent of 101 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9922833 | Charge trapping split gate embedded flash memory and associated methods | Mark T. Ramsbey, Chun Chen, Sameer Haddad, Kuo-Tung Chang, Unsoon Kim +2 more | 2018-03-20 |
| 9368393 | Line-edge roughness improvement for small pitches | — | 2016-06-14 |
| 8877641 | Line-edge roughness improvement for small pitches | — | 2014-11-04 |
| 8035153 | Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Fei Wang, Angela T. Hui, Alexander H. Nickel +4 more | 2011-10-11 |
| 7906807 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Angela T. Hui, Lei Xue, Harpreet Sachar, Phillip Jones +3 more | 2011-03-15 |
| 7776688 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Angela T. Hui, Lei Xue, Harpreet Sachar, Phillip Jones +3 more | 2010-08-17 |
| 7732276 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Fei Wang, Angela T. Hui, Alexander H. Nickel +4 more | 2010-06-08 |
| 7468296 | Thin film germanium diode with low reverse breakdown | Ercan Adem, Matthew S. Buynoski, Robert J. Chiu, Bryan K. Choo, Joong S. Jeon +5 more | 2008-12-23 |
| 7427457 | Methods for designing grating structures for use in situ scatterometry to detect photoresist defects | Marina V. Plat, Christopher F. Lyons, Anna M. Minvielle | 2008-09-23 |
| 7379924 | Quantifying and predicting the impact of line edge roughness on device reliability and performance | Amit P. Marathe | 2008-05-27 |
| 7309659 | Silicon-containing resist to pattern organic low k-dielectrics | Ramkumar Subramanian, Bhanwar Singh | 2007-12-18 |
| 7288487 | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure | Inkuk Kang, Hiroyuki Kinoshita | 2007-10-30 |
| 7279429 | Method to improve ignition in plasma etching or plasma deposition steps | Tzu-Yen Hsieh | 2007-10-09 |
| 7235414 | Using scatterometry to verify contact hole opening during tapered bilayer etch | Ramkumar Subramanian, Bhanwar Singh | 2007-06-26 |
| 7135396 | Method of making a semiconductor structure | Jeffrey A. Shields | 2006-11-14 |
| 7132306 | Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set | Seung-Hyun Rhee, Richard J. Huang | 2006-11-07 |
| 7052921 | System and method using in situ scatterometry to detect photoresist pattern integrity during the photolithography process | Marina V. Plat, Bhanwar Singh, Christopher F. Lyons, Scott A. Bell, Ramkumar Subramanian +1 more | 2006-05-30 |
| 6864184 | Method for reducing critical dimension attainable via the use of an organic conforming layer | — | 2005-03-08 |
| 6846749 | N-containing plasma etch process with reduced resist poisoning | Lynne A. Okada, Ramkumar Subramanian | 2005-01-25 |
| 6822291 | Optimized gate implants for reducing dopant effects during gate etching | Tammy Zheng, Emmanuel de Muizon, Linda Leard | 2004-11-23 |
| 6815359 | Process for improving the etch stability of ultra-thin photoresist | Uzodinma Okoroanyanwu | 2004-11-09 |
| 6811956 | Line edge roughness reduction by plasma treatment before etch | — | 2004-11-02 |
| 6794294 | Etch process that resists notching at electrode bottom | Tammy Zheng | 2004-09-21 |
| 6716571 | Selective photoresist hardening to facilitate lateral trimming | Harry J. Levinson, Uzodinma Okoroanyanwu | 2004-04-06 |
| 6713382 | Vapor treatment for repairing damage of low-k dielectric | Suzette K. Pangrle, Ecran Adem, Lynne A. Okada | 2004-03-30 |