Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6822291 | Optimized gate implants for reducing dopant effects during gate etching | Calvin T. Gabriel, Emmanuel de Muizon, Linda Leard | 2004-11-23 |
| 6794294 | Etch process that resists notching at electrode bottom | Calvin T. Gabriel | 2004-09-21 |
| 6605543 | Process to control etch profiles in dual-implanted silicon films | — | 2003-08-12 |
| 6541359 | Optimized gate implants for reducing dopant effects during gate etching | Calvin T. Gabriel, Emmanuel de Muizon, Linda Leard | 2003-04-01 |
| 6475922 | Hard mask process to control etch profiles in a gate stack | — | 2002-11-05 |
| 6399432 | Process to control poly silicon profiles in a dual doped poly silicon process | Subhas Bothra | 2002-06-04 |
| 6342428 | Method for a consistent shallow trench etch profile | Calvin T. Gabriel, Edward Yeh | 2002-01-29 |
| 6323113 | Intelligent gate-level fill methods for reducing global pattern density effects | Calvin T. Gabriel, Subhas Bothra, Harlan Lee Sur, Jr. | 2001-11-27 |
| 6306755 | Method for endpoint detection during dry etch of submicron features in a semiconductor device | — | 2001-10-23 |
| 6255226 | Optimized metal etch process to enable the use of aluminum plugs | Calvin T. Gabriel, Samit Sengupta | 2001-07-03 |
| 6251747 | Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices | Faran Nouri | 2001-06-26 |
| 6228757 | Process for forming metal interconnects with reduced or eliminated metal recess in vias | Samit Sengupta | 2001-05-08 |
| 6060376 | Integrated etch process for polysilicon/metal gate | Calvin T. Gabriel, Xi-Wei Lin, Linda Leard, Ian Robert Harvey | 2000-05-09 |