Issued Patents All Time
Showing 451–475 of 495 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6713358 | Method for making a semiconductor device having a high-k gate dielectric | Timothy E. Glassman, Christopher Parker, Matthew V. Metz, Lawrence Foley, Reza Arghavani +1 more | 2004-03-30 |
| 6696327 | Method for making a semiconductor device having a high-k gate dielectric | Justin K. Brask, Mark L. Doczy, John Barnak | 2004-02-24 |
| 6696345 | Metal-gate electrode for CMOS transistor applications | Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros | 2004-02-24 |
| 6667232 | Thin dielectric layers and non-thermal formation thereof | Steven J. Keating, Reza Arghavani, Jack T. Kavalieros, Douglas Barlage | 2003-12-23 |
| 6667251 | Plasma nitridation for reduced leakage gate dielectric layers | Robert McFadden, Jack T. Kavalieros, Reza Arghavani, Doug Barlage | 2003-12-23 |
| 6653700 | Transistor structure and method of fabrication | Jack T. Kavalieros, Anand S. Murthy, Brian Roberds, Brian S. Doyle | 2003-11-25 |
| 6645831 | Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide | Mohamad A. Shaheen, Beenyih Jin | 2003-11-11 |
| 6620713 | Interfacial layer for gate electrode and high-k dielectric layer and methods of fabrication | Reza Arghavani, Mark L. Doczy, Brian Roberds | 2003-09-16 |
| 6621131 | Semiconductor transistor having a stressed channel | Anand S. Murthy, Tahir Ghani, Kaizad Mistry | 2003-09-16 |
| 6617209 | Method for making a semiconductor device having a high-k gate dielectric | Reza Arghavani, Mark L. Doczy | 2003-09-09 |
| 6617210 | Method for making a semiconductor device having a high-k gate dielectric | Reza Arghavani | 2003-09-09 |
| 6610615 | Plasma nitridation for reduced leakage gate dielectric layers | Robert McFadden, Jack T. Kavalieros, Reza Arghavani, Doug Barlage | 2003-08-26 |
| 6597046 | Integrated circuit with multiple gate dielectric structures | Reza Arghavani, Bruce Beattie | 2003-07-22 |
| 6566727 | N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress | Reza Arghavani, Simon Shi-Ning Yang, John Graham | 2003-05-20 |
| 6541343 | Methods of making field effect transistor structure with partially isolated source/drain junctions | Anand S. Murthy, Patrick Morrow, Robert McFadden | 2003-04-01 |
| 6538278 | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | — | 2003-03-25 |
| 6518155 | Device structure and method for reducing silicide encroachment | Ebrahim Andideh, Mitch Taylor, Chia-Hong Jan, Julie Tsai | 2003-02-11 |
| 6514879 | Method and apparatus for dry/catalytic-wet steam oxidation of silicon | Reza Arghavani, Ron Dalesky | 2003-02-04 |
| 6373112 | Polysilicon-germanium MOSFET gate electrodes | Anand S. Murthy | 2002-04-16 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication | Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul Packan, Leopoldo D. Yau | 2001-12-04 |
| 6261925 | N2O Nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress | Reza Arghavani, Simon Shi-Ning Yang, John Graham | 2001-07-17 |
| 6221789 | Thin oxides of silicon | Reza Arghavani | 2001-04-24 |
| 6214679 | Cobalt salicidation method on a silicon germanium film | Anand S. Murthy | 2001-04-10 |
| 6198142 | Transistor with minimal junction capacitance and method of fabrication | Chia-Hong Jan, Paul Packan, Mitchell Taylor | 2001-03-06 |
| 6191016 | Method of patterning a layer for a gate electrode of a MOS transistor | Thomas A. Letson, Patricia Stokley, Peter K. Charvat, Ralph A. Schweinfurth | 2001-02-20 |