Issued Patents All Time
Showing 476–495 of 495 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6165826 | Transistor with low resistance tip and method of fabrication in a CMOS process | Chia-Hong Jan, Chan-Hong Chern, Leopoldo D. Yau | 2000-12-26 |
| 6153480 | Advanced trench sidewall oxide for shallow trench technology | Reza Arghavani, Binny Arcot | 2000-11-28 |
| 6140251 | Method of processing a substrate | Reza Arghavani, Weimin Han | 2000-10-31 |
| 6124171 | Method of forming gate oxide having dual thickness by oxidation process | Reza Arghavani, Bruce Beattie, Jack T. Kavalieros, Bob McFadden | 2000-09-26 |
| 6121100 | Method of fabricating a MOS transistor with a raised source/drain extension | Ebrahim Andideh, Lawrence N. Brigham, Tahir Ghani, Chia-Hong Jan, Justin S. Sandford +1 more | 2000-09-19 |
| 6087236 | Integrated circuit with multiple gate dielectric structures | Reza Arghavani, Bruce Beattie | 2000-07-11 |
| 6048769 | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | — | 2000-04-11 |
| 6046494 | High tensile nitride layer | Lawrence N. Brigham, Yung-Huei Lee, Raymond E. Cotner | 2000-04-04 |
| 5908313 | Method of forming a transistor | Chia-Hong Jan, Paul Packan, Mitchell Taylor | 1999-06-01 |
| 5891809 | Manufacturable dielectric formed using multiple oxidation and anneal steps | Lawrence N. Brigham, Chia-Hong Jan, Chan-Hong Chern, Binny Arcot | 1999-04-06 |
| 5856697 | Integrated dual layer emitter mask and emitter trench for BiCMOS processes | Stephen Chambers, Brian J. Brown, Chan-Hong Chern, Leopoldo D. Yau | 1999-01-05 |
| 5783478 | Method of frabricating a MOS transistor having a composite gate electrode | David B. Fraser, Kenneth Cadien, Gopal Raghavan, Leopoldo D. Yau | 1998-07-21 |
| 5780346 | N.sub.2 O nitrided-oxide trench sidewalls and method of making isolation structure | Reza Arghavani, Simon Shi-Ning Yang, John Graham | 1998-07-14 |
| 5763922 | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers | — | 1998-06-09 |
| 5710450 | Transistor with ultra shallow tip and method of fabrication | Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Paul Packan, Leopoldo D. Yau | 1998-01-20 |
| 5633202 | High tensile nitride layer | Lawrence N. Brigham, Yung-Huei Lee, Raymond E. Cotner | 1997-05-27 |
| 5625217 | MOS transistor having a composite gate electrode and method of fabrication | David B. Fraser, Kenneth Cadien, Gopal Raghavan, Leopoldo D. Yau | 1997-04-29 |
| 5488003 | Method of making emitter trench BiCMOS using integrated dual layer emitter mask | Stephen Chambers, Brian J. Brown, Chan-Hong Chern, Leopoldo D. Yau | 1996-01-30 |
| 5434093 | Inverted spacer transistor | Chan-Hong Chern, Shahriar Ahmed, Robert Hainsey, Robert J. Stoner, Todd E. Wilke +1 more | 1995-07-18 |
| 5244843 | Process for forming a thin oxide layer | William Hargrove, Leopoldo D. Yau | 1993-09-14 |