Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6720631 | Transistor having a deposited dual-layer spacer structure | Raymond E. Cotner, Makarem A. Hussein | 2004-04-13 |
| 6703672 | Polysilicon/amorphous silicon composite gate electrode | Chia-Hong Jan, Binglong Zhang | 2004-03-09 |
| 6380010 | Shielded channel transistor structure with embedded source/drain junctions | Richard Green, Ebrahim Andideh | 2002-04-30 |
| 6274913 | Shielded channel transistor structure with embedded source/drain junctions | Richard Green, Ebrahim Andideh | 2001-08-14 |
| 6121100 | Method of fabricating a MOS transistor with a raised source/drain extension | Ebrahim Andideh, Robert S. Chau, Tahir Ghani, Chia-Hong Jan, Justin S. Sandford +1 more | 2000-09-19 |
| 6046494 | High tensile nitride layer | Yung-Huei Lee, Robert S. Chau, Raymond E. Cotner | 2000-04-04 |
| 6017819 | Method for forming a polysilicon/amorphous silicon composite gate electrode | Chia-Hong Jan, Binglong Zhang | 2000-01-25 |
| 5911111 | Polysilicon polish for patterning improvement | Mark Bohr, Peter K. Moon, Seiichi Morimoto | 1999-06-08 |
| 5891809 | Manufacturable dielectric formed using multiple oxidation and anneal steps | Robert S. Chau, Chia-Hong Jan, Chan-Hong Chern, Binny Arcot | 1999-04-06 |
| 5714413 | Method of making a transistor having a deposited dual-layer spacer structure | Raymond E. Cotner, Makarem A. Hussein | 1998-02-03 |
| 5633202 | High tensile nitride layer | Yung-Huei Lee, Robert S. Chau, Raymond E. Cotner | 1997-05-27 |
| 5091332 | Semiconductor field oxidation process | Mark Bohr, Shahab Hossaini | 1992-02-25 |