Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6191016 | Method of patterning a layer for a gate electrode of a MOS transistor | Robert S. Chau, Thomas A. Letson, Patricia Stokley, Peter K. Charvat | 2001-02-20 |
| 5933759 | Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications | Phi L. Nguyen, Swaminathan Sivakumar | 1999-08-03 |
| 5843846 | Etch process to produce rounded top corners for sub-micron silicon trench applications | Phi L. Nguyen | 1998-12-01 |