Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7008872 | Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures | Valery M. Dubin, Chin-Chang Cheng, Makarem A. Hussein, Ruth A. Brain | 2006-03-07 |
| 6968532 | Multiple exposure technique to pattern tight contact geometries | Swaminathan Sivakumar, Rex Frost | 2005-11-22 |
| 6958547 | Interconnect structures containing conductive electrolessly deposited etch stop layers, liner layers, and via plugs | Valery M. Dubin, Chin-Chang Cheng, Makarem A. Hussein, Ruth A. Brain | 2005-10-25 |
| 6472315 | Method of via patterning utilizing hard mask and stripping patterning material at low temperature | Lawrence Wong | 2002-10-29 |
| 6001699 | Highly selective etch process for submicron contacts | Mark A. Fradkin, Gilroy Vandentop | 1999-12-14 |
| 5933759 | Method of controlling etch bias with a fixed lithography pattern for sub-micron critical dimension shallow trench applications | Ralph A. Schweinfurth, Swaminathan Sivakumar | 1999-08-03 |
| 5843846 | Etch process to produce rounded top corners for sub-micron silicon trench applications | Ralph A. Schweinfurth | 1998-12-01 |