Issued Patents All Time
Showing 101–125 of 552 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10600778 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2020-03-24 |
| 10586854 | Gate-all-around field effect transistor having multiple threshold voltages | Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo Vega | 2020-03-10 |
| 10586855 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Hui Zang | 2020-03-10 |
| 10566443 | Nanosheet transitor with optimized junction and cladding defectivity control | Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Chun-Chen Yeh | 2020-02-18 |
| 10566438 | Nanosheet transistor with dual inner airgap spacers | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2020-02-18 |
| 10566442 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2020-02-18 |
| 10546776 | Dual silicide liner flow for enabling low contact resistance | Praneet Adusumilli, Veeraraghavan S. Basker, Zuoguang Liu, Chun-Chen Yeh | 2020-01-28 |
| 10546942 | Nanosheet transistor with optimized junction and cladding defectivity control | Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Chun-Chen Yeh | 2020-01-28 |
| 10541318 | Prevention of extension narrowing in nanosheet field effect transistors | Chun Wing Yeung, Chen Zhang | 2020-01-21 |
| 10535606 | Dual metal-insulator-semiconductor contact structure and formulation method | Takashi Ando, Hiroaki Niimi | 2020-01-14 |
| 10510617 | CMOS VFET contacts with trench solid and liquid phase epitaxy | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2019-12-17 |
| 10490653 | Embedded bottom metal contact formed by a self-aligned contact process for vertical transistors | Su Chen Fan, Zuoguang Liu, Heng Wu | 2019-11-26 |
| 10468525 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2019-11-05 |
| 10453939 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh | 2019-10-22 |
| 10453922 | Conformal doping for punch through stopper in fin field effect transistor devices | Huiming Bu, Sivananda K. Kanakasabapathy, Fee Li Lie | 2019-10-22 |
| 10439045 | Flipped VFET with self-aligned junctions and controlled gate length | Chen Zhang | 2019-10-08 |
| 10439031 | Integration of vertical-transport transistors and electrical fuses | Ruilong Xie, Kangguo Cheng, Chun-Chen Yeh | 2019-10-08 |
| 10418485 | Forming a combination of long channel devices and vertical transport Fin field effect transistors on the same substrate | Cheng Chi, Chen Zhang | 2019-09-17 |
| 10418277 | Air gap spacer formation for nano-scale semiconductor devices | Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta +2 more | 2019-09-17 |
| 10411127 | Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate | Cheng Chi, Chen Zhang | 2019-09-10 |
| 10396177 | Prevention of extension narrowing in nanosheet field effect transistors | Chun Wing Yeung, Chen Zhang | 2019-08-27 |
| 10396183 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Chun-Chen Yeh, Hui Zang | 2019-08-27 |
| 10396000 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Chun-Chen Yeh, Hui Zang | 2019-08-27 |
| 10396178 | Method of forming improved vertical FET process with controlled gate length and self-aligned junctions | Chen Zhang | 2019-08-27 |
| 10396208 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Chun-Chen Yeh | 2019-08-27 |